Walter Scott, Jr. College of Engineering

Graduate Exam Abstract

Prasanna Ramakrishna
M.S. Final
Dec 07, 2007, 2:00 PM
Engineering B105
Binning of Devices with X-IDDQ
Abstract: The idea behind IDDQ testing is that the non-defective CMOS circuits have no static current paths, whereas for the circuits with certain defects such as gate oxide shorts, bridging faults, etc. and for the circuits which are likely to fail, there could be high leakage paths when the right excitation is applied. Traditional IDDQ testing uses a threshold to distinguish between the good and bad ICs. With the advancement in IC fabrication technologies towards the deep sub-micron level, the shrinking of geometries have resulted in a higher leakage currents which have made it difficult to distinguish between faulty and a fault-free device. These problems associated with the static threshold limit setting approaches have led to the need for alternative methods of IDDQ testing to ensure its applicability in the future. Several statistical approaches have been proposed in order to screen defective devices in the manufacturing lots. X-IDDQ is one such existing statistical technique used for detecting defects in the manufacturing lots. This thesis performs an analysis of the X-IDDQ technique and proposes an enhancement to the existing binning strategy. X-IDDQ technique reduces the dimensionality of the IDDQ vectors into a single statistic X. The X-statistic can be used to screen ICs with various IDDQ and non-IDDQ faults. Thus with the knowledge of the IDDQ measurements alone, a significant fraction of devices that fail various kinds of IDDQ and non-IDDQ tests can be eliminated without subjecting devices to further testing thereby reducing the overall test effort. In this work, an analysis of the existing divide-by-three binning is performed and the binning strategy is evaluated. An effort is made to reduce the test effort by improving the overall efficiency of the binning technique. X-IDDQ technique depends on a set of prescreened devices called the training set. The sensitivity of the binning technique to the training set is analyzed. Previous work on X-IDDQ technique introduced the concept, but certain important aspects such as the selection of the principal components for calculating X-IDDQ and its impact on the test effort were not evaluated. The research presented in this work aims at evaluating alternatives for the binning scheme and the sensitivity of X-IDDQ. In addition to evaluating the divide-by-three binning scheme, this work also introduces a new binning technique called extended binning. With the extended-binning technique, it is possible to use X-IDDQ as an online binning strategy under certain conditions more effectively than with the divide-by-three binning technique. The extended-binning and the divide-by-three binning techniques are evaluated using the SEMATECH benchmark data and also on artificially generated lots which closely resemble the practical IC manufacturing lots, and the results suggest that the extended-binning technique could be as efficient as or better than the naive divide-by-three binning approach. The burn-in analysis performed suggests that the extended binning technique helps in reducing the required test effort. The online-binning scheme discussed in this work can be used for implementing production line testing and real time binning of devices which allows fast and real time sorting of ICs in production using the IDDQ test methodology.
Adviser: Dr. Anura P. Jayasumana
Co-Adviser: Dr. Yashwant K. Malaiya
Non-ECE Member: Dr. Yashwant K. Malaiya
Member 3: Dr. Steven C. Reising
Addional Members:
Program of Study: