Walter Scott, Jr. College of Engineering

Graduate Exam Abstract

Nishit Kapadia
Ph.D. Qualifying
Feb 13, 2012, 10 am
Engr C101B
N/A - qualifying exam
Abstract: qualifying exam
Adviser: Suddep Pasricha
Co-Adviser: N/A
Non-ECE Member: Dr. Michelle Strout (Computer Science Dept.)
Member 3: Dr. Anura Jayasumana
Addional Members: Dr. H. J. Siegel,N/A
1) N. Kapadia, S. Pasricha, “VISION: A Framework for Voltage Island Aware Synthesis of Interconnection Networks-on-Chip”, ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2011. 2) N. Kapadia, S. Pasricha, “A Framework for Low Power Synthesis of Interconnection Networks-on-Chip with Multiple Voltage Islands”, Integration, the VLSI Journal. 3)N. Kapadia, S. Pasricha, “A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands”, IEEE International Conference on VLSI Design (VLSID), January 2012.

Publications to be Reviewed:
Chemical-Mechanical Polishing Aware Application-Specific 3D NoC Design

PM-COSYN: PE and Memory Co-Synthesis for MPSoCs

Program of Study:
ECE 661
ECE 658
ECE 526 (tranferred from SIUC)
ECE 528 (tranferred from SIUC)
CS 5321 (tranferred from MTU)
EE 5900 (tranferred from MTU)