Walter Scott, Jr. College of Engineering

Graduate Exam Abstract

Rajbharath Chandramohan
M.S. Final
Dec 09, 2016, 1:00 pm - 3:00 pm
CSB 425
Hardware Implementation and Design Space Exploration for Wave 2D and Jacobi 2D Stencil Computations
Abstract: Hardware accelerators are highly
optimized functional blocks designed
to perform specific tasks at a higher
performance and better energy
efficiency. We developed a hardware
accelerator for two common 2-D
“stencil” computations: Jacobi-2D and
Wave 2D. They are used in many
scientific applications in the field of
acoustics, electro magnetics and Fluid
dynamics. These problems have
large problem sizes, and memory
limitations and bandwidth constraints
result in long run times on large
problems. Hence, We developed an
approach which increases the
performance. We designed a parallel
circuit to accelerate these programs
and developed analytical models for
the performance (execution time),
bandwidth and area of these
accelerators. We solved the
corresponding optimization problems
analytically and symbolically using
MATLAB and Excel Solver.

We split the computation into two
levels of tiling. The first level called
passes is a vertical rectangular prism
that runs through the 3-D iteration
space. Each pass is mapped to a grid
of PEs in the hardware accelerator.
The second level of tiling splits the
vertical prism into smaller prisms
executed by a PE. The resulting
architecture is implemented in verilog
using Altera Quartus and simulated
using ModelSIM. Results from
ModelSIM provides a more accurate
model and a experimental verification
of the design. We also achieved
improved performance, lower
Bandwidth and energy consumption.
Adviser: Rajbharath Chandramohan
Co-Adviser: N/A
Non-ECE Member: Sudeep Pasricha, Department of Electrical and Computer Engineering
Member 3: Oliver Pinaud, Department of Mathematics
Addional Members: N/A
Program of Study: