Walter Scott, Jr. College of Engineering

Graduate Exam Abstract

Srinivas Desai
M.S. Final
Nov 07, 2014, 10:00 am - 12:00 pm
Dean's Conference Room B214
Design and Analysis of Energy-Efficient Hierarchical Electro-Photonic Network-On-Chip Architectures
Abstract: Future applications running on chip multiprocessors (CMPs) with tens to hundreds of cores on a chip will require an efficient inter-core communication strategy to achieve high performance. With recent demonstrations of feasibility in fabricating photonic components for on-chip communication, researchers are now focusing on photonic communication based on-chip networks for future CMPs. Photonic on-chip interconnects offers several benefits over conventional electrical on-chip interconnects, such as (1) high-bandwidth support by making use of dense wavelength division multiplexing, (2) distance independent power consumption, (3) significantly lower latency, (4) improved performance-per-watt. Owing to these advantages, it is expected that designers will use photonic interconnections to augment existing electrical networks, to realize scalable and efficient on-chip networks for future CMPs. In this thesis, we design and explore a hierarchical electro-photonic network-on-chip architecture called NOVA. NOVA aims to optimize several key design metrics such as system throughput, latency, and energy-delay-product which determine the overall system performance of a CMP. NOVA has three levels of communication hierarchy that are independent of one another. The first level has a broadband-resonator based wavelength switch. The second level consists of a low loss silicon nitride arrayed waveguide grating based custom router. The last level of the hierarchy is made up of photonic ring waveguides. We modeled and simulated multiple configurations of the proposed architecture with different designs of the wavelength switch, and various arbitration techniques on the photonic rings. This comprehensive analysis of NOVA allows us to arrive at an optimal configuration of the network for a given set of input applications and CMP platform. Finally, experimental results indicate a strong motivation for considering the proposed architecture, as the improvements in the throughput and energy-delay product were up to 10.15× and 11.02×, respectively, compared to other state-of-the-art photonic network-on-chip architectures.
Adviser: Sudeep Pasricha
Co-Adviser: N/A
Non-ECE Member: Yashwant K. Malaiya
Member 3: Sanjay Rajopadhye
Addional Members: N/A
Program of Study:
ECE 450, 451
ECE 554
ECE 561
ECE 565
ECE 571, 575
ECE 699
GRAD 511