Walter Scott, Jr. College of Engineering

Graduate Exam Abstract

Abstract: Abstract 1—Recent changes in technology market demand faster turn around of IC design and as a result, designers struggle to meet performance requirements under prohibitively expensive non-recurring engineering (NRE) costs. Increasing costs for design, validation, and time to market, are most concerning issues for new systems. While past generations of microprocessors had more custom circuit design to meet tighter cycle time battle, more startups and IC companies are trying to design by moving towards common synthesizable design methodology and most cases sacrificing desired speed of the chip in favor of new functionality and time to market. In this paper, we propose a synthesis based physical design methodology, using soft hierarchy, interior pin placement, pre-placing critical logic, post routing techniques etc on a very timing and area challenged unit, L2 cache. Our experimental results include analysis of congestions, timing take down, power and routing resources of the design. With the proposed design methodology we show that both development time and cost can be cut by about 50% without compromising significant design quality.

Abstract 2- Recent changes in technology market demand to support multi clock and multi power domain interfacing both on and off chip IP in high speed design environment. In a custom circuit design methodology, designers carefully hand craft gates to support multi domains satisfying required timing and methodology requirements. However, in a synthesis design environment, designers struggle to make sure these interfaces were designed and timed correctly. Similarly, muxing multi clocks to support design testability and gating clocks to support low power design in synthesis methodology is a big challenge today. In this paper, we show a synthesis based physical design methodology on multi clock and power domain area, and show how this interface can be timed. We also, show how multi clock can be handled to support testability and low power circuit design.
Adviser: Prof. Tom Chen
Co-Adviser: N/A
Non-ECE Member: Prof. Yashwant Malaiya, CS
Member 3: Dr. Sudeep Pasricha, ECE
Addional Members: Dr. Ali Pezeshki, ECE
Submitted to TCAD: Synthesis Based Design and Implementation Methodology of High Speed, High Performing Unit: L2 Cache Unit Design
Program of Study:
EE 660
EE 581
EE 571
EE 554
EE 5765 (CUNY)
EE 5723 (CUNY
EE 244 (GWU)
EE 251 (GWU)