Walter Scott, Jr. College of Engineering

Graduate Exam Abstract

Nishi Kapadia
Ph.D. Preliminary
Nov 26, 2012, 9:30 am
ISTeC Conference Room - CS305
A Holistic Framework for Multi-objective Synthesis of 2D and 3D NoC-based MPSoCs with Voltage Islands
Abstract: High power dissipation has today become one of the major
challenges in multiprocessor system-on-chip (MPSoC) design.
The use of voltage islands (VIs) can help reduce both
switching and standby components of power. However, with
increasing core counts in MPSoCs, the complexity of problems
such as core to VI-mapping and VI-aware network-on-chip (NoC)
design for optimal performance and power has grown
exponentially. Moreover, undesirable IR drops in Power
Delivery Networks (PDNs) of these systems can worsen the
quality of voltage supply and thereby affect overall
performance. This problem is even more severe in 3D MPSoCs
where the current in the PDN increases proportionally to the
number of device layers. Additionally, with nanometer-scale
feature sizes in today’s CMOS technologies, variations in
fabrication processes have been observed to cause
unpredictable behavior in contemporary MPSoC designs. System-
level design approaches that are aware of these variations
can be crucial for designing energy-efficient systems. To
overcome these challenges, we propose a holistic NoC
synthesis framework for emerging MPSoCs. Our framework
combines novel VI-aware algorithms and heuristics to perform
VI partitioning, core-to-die mapping, and routing path
allocation to minimize chip power dissipation; at the same
time satisfying application performance and VI-contiguity
constraints. A novel PDN-aware methodology integrates these
NoC-design algorithms with efficient PDN synthesis techniques
which optimize the PDN design while satisfying IR-drop
constraints, to achieve an improved overall system
performance and power profile. Finally, a variation-aware
methodology is proposed that together with a novel VI-
placement approach optimizes computation energy of the MPSoC
in the presence of process variations. Experimental results
show that our framework derives significant improvements over
prior efforts in the area of NoC synthesis for MPSoCs.
Adviser: Dr. Sudeep Pasricha
Co-Adviser: N/A
Non-ECE Member: Dr. Michelle Strout, Computer Science
Member 3: Dr. Anura Jayasumana
Addional Members: Dr. H. J. Siegel
N. Kapadia, S. Pasricha, “VISION: A Framework for Voltage Island Aware Synthesis of Interconnection Networks-on-Chip”, ACM Great Lakes Symposium on VLSI (GLSVLSI) 2011, May 2011.

N. Kapadia, S. Pasricha, “A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands”, IEEE International Conference on VLSI Design (VLSID), January 2012.

N. Kapadia, S. Pasricha, “A Framework for Low Power Synthesis of Interconnection Networks-on-Chip with Multiple Voltage Islands”, the Integration, the VLSI Journal.
Program of Study:
ECE 658
ECE 661