Graduate Exam Abstract

Abstract: This PhD thesis addresses two major areas in the design, characterization, and optimization of photonic processors and memories.

First, we explore the fundamentals of phase-change materials (PCMs) and how their behavior can be modeled when integrated with silicon photonic devices to implement reconfigurable photonic components. These components can be tuned to suit various applications. Leveraging the unique non-volatile optical properties of PCMs, we propose a design-space exploration for their co-integration with silicon photonics to realize photonic memory devices with zero static power consumption. This is crucial for eliminating the need for electrical-to-optical (E-O) and optical-to-electrical (O-E) conversions for weight readout when being used in optical computing systems, paving the way toward a fully optical and energy-efficient computing ecosystem. We propose a bottom-up framework to design a novel photonic linear multiplier using tunable directional couplers (DCs) integrated with PCMs. To address the slow response and high-power consumption of the PCM-based photonic devices, including photonic memories, we characterize a new type of PCM with birefringence properties. Such a material shows anisotropic optical properties and can change the group delay and polarisation of interacting polarized electromagnetic waves. Starting from this, we propose polarisation encodable photonic memories and photonic computing units using 2D ferroelectric material whose their phase change can happen in order of nanoseconds, which is aligned with the phonon dispersion relation.

Second, we propose a novel fully programmable linear photonic processor, which we call LightPro, with improved scalability, performance, and footprint. At the heart of LightPro are compact, low-loss, and programmable SiPh directional coupler (DC) devices that deploy phase-change material (PCM) for programming the DC's splitting ratio. By thermally inducing phase transitions in the PCM, the coupling coefficient of the DC can be dynamically adjusted to achieve different splitting ratios in the device output. Building on this device foundation, we develop a neural architecture search (NAS) and pruning algorithm to optimize the architecture of the processor for performing MVM operations. Additionally, we address the challenges in designing coherent photonic multipliers that rely on single-frequency operation and optical interference through cascaded networks of Mach-Zehnder Interferometers (MZIs). Specifically, we model the accumulated effects of optical loss, crosstalk, and fabrication process variations (FPVs) in silicon photonic devices—particularly in MZIs—and analyze how these imperfections impact system-level performance when scaled to implement coherent silicon photonic neural networks.
Our findings indicate that network accuracy can degrade by up to 85\% due to the cumulative effects of optical loss, crosstalk, and phase noise resulting from FPVs. To address these limitations, we propose robust and optimized silicon photonic device designs that can partially mitigate such issues at the design stage.

Adviser: Mahdi Nikdast
Co-Adviser: Sudeep Pasricha
Non-ECE Member: Edwin Chong
Member 3: Nikhil Krishnaswamy
Addional Members: Sudeep Pasricha

Publications:
https://scholar.google.com/citations?user=CYVnaLQAAAAJ&hl=en&oi=ao

Program of Study:
ECE-544
ECE-520
ECE-506
ECE-528
ECE-574
ECE-673
ECE-799
ECE-799