Asif Anwar Baig Mirza
Ph.D. PreliminaryAug 16, 2022, 10:00 am - 12:00 pm
Zoom Meetings
Design Exploration and Optimization of Silicon Photonic Integrated Circuits under Fabrication-Process Variations
Abstract: Silicon photonic integrated circuits (PICs) have become a key solution to handle the growing demands of large data transmission in emerging applications by consuming less power and low heat dissipation while offering ultra-high data bandwidth than electronic circuits. With Moore’s Law slowing down and the end of Dennard scaling, PICs offer a logical step to improve data movement and processing performance in future computing systems. On PICs, light is processed and routed by means of optical waveguides. Silicon has a unique feature of high refractive index contrast in the silicon-on-insulator (SOI) platform which allows for tight confinement of light in nanometer waveguide cores and bends with a radius of only a few microns. PICs comprise of a diverse set of elements such as waveguide splitters, combiners, crossings, and couplers which help with distribution, routing, and computation of optical signals. Optical signals are converted to electrical signals with the help of photodiodes which in silicon photonics are implemented using Germanium. To enable PICs for wavelength-division multiplexing (WDM), there is a need for efficient wavelength filters consisting of optical delay lines or resonators. Optical delay lines are usually built using Mach-Zehnder Interferometers (MZIs) which consists of a splitter, two waveguides with a given group delay, and a combiner. Microring resonators (MRRs) can be used as wavelength filters when the input wavelength matches a whole multiple times in the circumference of the ring. Other components such as grating coupler help couple the light into and out of a PIC. PICs can be fabricated on the infrastructure developed for complimentary metal–oxide–semiconductor (CMOS) electronics. This technology now enables deep submicron features with unprecedented accuracy in large volumes along with close integration of photonics and electronic circuits. The use of silicon as a base material makes reuse of these manufacturing tools possible, but photonics imposes different demands on the processes.
Although silicon photonics offers data transmission and computation at light speed with high bandwidth and low power consumption, the fundamental building blocks in PICs (e.g., optical waveguides) are extremely sensitive to nanometer-scale fabrication-process variations (FPVs) caused due to slight randomness in optical lithography processes. Active compensation by the means of electronic circuits (a.k.a. tuning) is necessary to compensate for FPVs. Tunable microheaters can be used for active compensation which affect the material properties of silicon to improve PIC’s performance under FPVs. However, the total power consumed due to tuning in a working PIC can be drastically high. For example, variations as small as 1 nm in an MRR can deviate the optical frequency response of the device by 2 nm that leads to approximately 25% increase in the tuning power consumption to compensate for variations of a single MRR. Additionally, a system can have thousands of such MRRs that can easily add up the total power consumption of the system. In order to address FPVs we need to observe the reliability not just at a system level but down to the device level by enabling reliable, FPV-aware devices to enable FPV-resilient PICs and photonic systems. Designing more reliable and FPV-tolerant photonic devices should not only help us with reducing the total power consumption but also build more reliable circuits with fault-free operational behavior for data transmission and computation in future computing systems.
In this PhD thesis, we study two of the major silicon photonic devices widely employed in PICs, MRRs and MZIs, to develop design techniques targeting improving the device tolerance towards FPVs caused due to uncertainties in optical lithography processes. We take a bottom-up approach in improving the reliability of a PIC. We propose improved MRR designs which can be used in any PIC to reduce the overall shift in the resonant wavelength of the device due to fabrication-process variations, further reducing the total power consumption required to tune the device. We found various applications for such variation-aware photonic devices and show up to 70% reduction in power consumption in photonic circuits using the optimized devices. Furthermore, we study the impact of having such improved designs in photonic artificial intelligence (AI) hardware accelerators and how they can improve the network accuracy and the overall power consumption. With MZIs we perform a comprehensive analysis of the impact of FPVs on coherent photonic neural networks. By improving the design of MZIs we study the impact of network accuracy under FPVs with different distributions and correlations. Finally, we also compile our work into a device exploration tool that allows the user to set design parameters in an MRR and study its behavior under different fabrication-process variation profiles. With this tool we aim to give the user the power to determine desired MRR designs based on user-defined design and performance requirements and budget constraints set on a photonic system.
Although silicon photonics offers data transmission and computation at light speed with high bandwidth and low power consumption, the fundamental building blocks in PICs (e.g., optical waveguides) are extremely sensitive to nanometer-scale fabrication-process variations (FPVs) caused due to slight randomness in optical lithography processes. Active compensation by the means of electronic circuits (a.k.a. tuning) is necessary to compensate for FPVs. Tunable microheaters can be used for active compensation which affect the material properties of silicon to improve PIC’s performance under FPVs. However, the total power consumed due to tuning in a working PIC can be drastically high. For example, variations as small as 1 nm in an MRR can deviate the optical frequency response of the device by 2 nm that leads to approximately 25% increase in the tuning power consumption to compensate for variations of a single MRR. Additionally, a system can have thousands of such MRRs that can easily add up the total power consumption of the system. In order to address FPVs we need to observe the reliability not just at a system level but down to the device level by enabling reliable, FPV-aware devices to enable FPV-resilient PICs and photonic systems. Designing more reliable and FPV-tolerant photonic devices should not only help us with reducing the total power consumption but also build more reliable circuits with fault-free operational behavior for data transmission and computation in future computing systems.
In this PhD thesis, we study two of the major silicon photonic devices widely employed in PICs, MRRs and MZIs, to develop design techniques targeting improving the device tolerance towards FPVs caused due to uncertainties in optical lithography processes. We take a bottom-up approach in improving the reliability of a PIC. We propose improved MRR designs which can be used in any PIC to reduce the overall shift in the resonant wavelength of the device due to fabrication-process variations, further reducing the total power consumption required to tune the device. We found various applications for such variation-aware photonic devices and show up to 70% reduction in power consumption in photonic circuits using the optimized devices. Furthermore, we study the impact of having such improved designs in photonic artificial intelligence (AI) hardware accelerators and how they can improve the network accuracy and the overall power consumption. With MZIs we perform a comprehensive analysis of the impact of FPVs on coherent photonic neural networks. By improving the design of MZIs we study the impact of network accuracy under FPVs with different distributions and correlations. Finally, we also compile our work into a device exploration tool that allows the user to set design parameters in an MRR and study its behavior under different fabrication-process variation profiles. With this tool we aim to give the user the power to determine desired MRR designs based on user-defined design and performance requirements and budget constraints set on a photonic system.
Adviser: Mahdi Nikdast
Co-Adviser: Sudeep Pasricha
Non-ECE Member: Samuel Brewer
Member 3: Jesse Wilson
Addional Members: N/A
Co-Adviser: Sudeep Pasricha
Non-ECE Member: Samuel Brewer
Member 3: Jesse Wilson
Addional Members: N/A
Publications:
A. Mirza, F. Sunny, P. Walsh, K. Hassan, S. Pasricha, and M. Nikdast, “Silicon photonic microring resonators: A comprehensive design-space exploration and optimization under fabrication-process variations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2021.
A. Shafiee, A. Mirza, F. Sunny, S. Banerjee, K. Chakrabarty, S. Pasricha, and M. Nikdast, “Inexact silicon photonics: From devices to applications,” to appear, OSA Photonics in Switching and Computing (PSC) Conference, 2021. (Invited)
F. Sunny, A. Mirza, M. Nikdast, and S. Pasricha, “ROBIN: A robust optical binary neural network accelerator,” to appear, IEEE/ACM International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), 2021.
F. Sunny, A. Mirza, M. Nikdast, and S. Pasricha, “CrossLight: A cross-layer optimized silicon photonic neural network accelerator,” to appear, IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, December 2021.
A. Mirza, S. Pasricha, and M. Nikdast, “Variation-Aware Inter-Device Matching in Silicon Photonic Microring Resonator Demultiplexers,” IEEE Photonics Conference (IPC), 2020
F. Sunny, A. Mirza, I. Thakkar, S. Pasricha, and M. Nikdast, “LORAX: Loss-Aware Approximations for Energy-Efficient Silicon Photonic Networks-on-Chip”, ACM Great Lakes Symposium on VLSI (GLSVLSI), 2020.
A. Mirza, F. Sunny, S. Pasricha, and M. Nikdast, “Silicon Photonic Microring Resonators: Design Optimization under Fabrication Non-uniformity”, IEEE/ACM Design, Automation and Test in Europe (DATE) Conference and Exhibition, March 2020.
A. Mirza, S. Manafi Avari, E. Taheri, S. Pasricha, and M. Nikdast, “Promise of cross-layer design in high-performance computing systems integrating silicon photonics”, IEEE/ACM Design, Automation and Test in Europe (DATE) Conference and Exhibition, March 2020.
A. Mirza, F. Sunny, P. Walsh, K. Hassan, S. Pasricha, and M. Nikdast, “Silicon photonic microring resonators: A comprehensive design-space exploration and optimization under fabrication-process variations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2021.
A. Shafiee, A. Mirza, F. Sunny, S. Banerjee, K. Chakrabarty, S. Pasricha, and M. Nikdast, “Inexact silicon photonics: From devices to applications,” to appear, OSA Photonics in Switching and Computing (PSC) Conference, 2021. (Invited)
F. Sunny, A. Mirza, M. Nikdast, and S. Pasricha, “ROBIN: A robust optical binary neural network accelerator,” to appear, IEEE/ACM International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), 2021.
F. Sunny, A. Mirza, M. Nikdast, and S. Pasricha, “CrossLight: A cross-layer optimized silicon photonic neural network accelerator,” to appear, IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, December 2021.
A. Mirza, S. Pasricha, and M. Nikdast, “Variation-Aware Inter-Device Matching in Silicon Photonic Microring Resonator Demultiplexers,” IEEE Photonics Conference (IPC), 2020
F. Sunny, A. Mirza, I. Thakkar, S. Pasricha, and M. Nikdast, “LORAX: Loss-Aware Approximations for Energy-Efficient Silicon Photonic Networks-on-Chip”, ACM Great Lakes Symposium on VLSI (GLSVLSI), 2020.
A. Mirza, F. Sunny, S. Pasricha, and M. Nikdast, “Silicon Photonic Microring Resonators: Design Optimization under Fabrication Non-uniformity”, IEEE/ACM Design, Automation and Test in Europe (DATE) Conference and Exhibition, March 2020.
A. Mirza, S. Manafi Avari, E. Taheri, S. Pasricha, and M. Nikdast, “Promise of cross-layer design in high-performance computing systems integrating silicon photonics”, IEEE/ACM Design, Automation and Test in Europe (DATE) Conference and Exhibition, March 2020.
Program of Study:
ECE 554
ECE 580B9
ECE 581C1
ECE 656
GRAD 580A2
N/A
N/A
N/A
ECE 554
ECE 580B9
ECE 581C1
ECE 656
GRAD 580A2
N/A
N/A
N/A