The EPIC Lab’s research on memory optimizations for manycore computing spans a rich cross‑layer exploration of emerging memory technologies, near‑memory and in‑memory processing, and intelligent memory system design for high‑performance, energy‑efficient architectures. This work introduces novel frameworks for computation offloading and load balancing in near‑memory systems, dynamic and variation‑aware phase‑change memory architectures, and hybrid DRAM/PCM designs that improve latency, endurance, and refresh efficiency. The lab has advanced optical and photonic memory concepts—including PCM‑based photonic memories, optical processing‑in‑memory, and cross‑layer optimized photonic main memory architectures—to address the bandwidth and energy bottlenecks of modern AI and manycore workloads. Complementary contributions include approximate memory controllers for GPGPUs, hybrid last‑level cache designs, 3D‑integrated DRAM optimizations, and adaptive scratchpad memory management for multimedia and embedded applications. Collectively, this research establishes a comprehensive foundation for scalable, energy‑aware, and application‑optimized memory subsystems that meet the demands of next‑generation heterogeneous and manycore computing platforms.
Selected Publications
S. Maity, M. Ghose, S. Pasricha, “A Framework for Near Memory Processing with Computation Offloading and Load Balancing”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025
A. Shafiee, Y. Jie, B. Charbonnier, S. Pasricha, M. Nikdast, “Programmable Phase Change Materials and Silicon Photonics Co-integration for Photonic Memory Applications: A Systematic Study”, Journal of Optical Microsystems Letters, 2024.
F. Sunny, A. Shafiee, B. Charbonnier, M. Nikdast, S. Pasricha, “COMET: A Cross-Layer Optimized Optical Phase Change Main Memory Architecture”, IEEE/ACM DATE, Mar 2024.
F. Sunny, A. Shaifee, A. Balasubramaniam, M. Nikdast, S. Pasricha, “OPIMA: Optical Processing-In-Memory for Convolutional Neural Network Acceleration”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.
A. Shafiee, S. Pasricha, M. Nikdast, “Design-Space Exploration in PCM-based Photonic Memory”, ACM GLSVLSI, 2023.
K. Khan, S. Pasricha, R. G. Kim, “A Survey of Resource Management for Processing-in-Memory and Near-Memory Processing Architectures”, Journal of Low Power Electronics and Applications, Special Issue on Design Space Exploration and Resource Management of Multi/Many-Core Systems, Sep 2020.
V. Y. Raparti, S. Pasricha, “Approximate NoC and Memory Controller Architectures for GPGPU Accelerators“, IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol. 31, Iss 5., May 2020.
S. Bhosale, S. Pasricha, “SLAM: High Performance and Energy Efficient Hybrid Last Level Cache Architecture for Multicore Embedded Systems,” IEEE International Conference on Embedded Software and Systems (ICESS), Las Vegas, NV, USA, Jun. 2019
I. Thakkar, S. Pasricha, “DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency and Restorable Endurance”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (TCAD), Volume: 37, Issue: 9 , Sept. 2018.
I. Thakkar, S. Pasricha, “DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency,” IEEE International Conference on VLSI Design (VLSID), Jan 2017.
I. Thakkar, S. Pasricha, “Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube Architectures,” IEEE International Conference on VLSI Design (VLSID), Jan 2016.
I. Thakkar, S. Pasricha, “A Novel 3D Graphics DRAM Architecture for High-Performance and Low-Energy Memory Accesses,” IEEE International Conference on Computer Design (ICCD), Oct 2015.
S. Pasricha, I. Thakkar, “Re-architecting DRAM memory systems with 3D Integration and Photonic Interfaces”, Memory Architecture and Organization Workshop (MeAOW), Oct 2014 (Invited)
L. Bathen, Y. Ahn, S. Pasricha, N. Dutt, “MultiMaKe: Chip-Multiprocessor Driven Memory-aware Kernel Pipelining”, ACM Transactions on Embedded Computing Systems (TECS), 12(1), Mar 2013.
D. Cho, S. Pasricha, I. Issenin, N. Dutt, Y. Paek , “Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications“, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (TCAD), Vol. 28, No. 4, pp. 554-567, Apr 2009
L. A. D. Bathen, N. Dutt, S. Pasricha, “A Framework for Memory-aware Multimedia Application Mapping on Chip-Multiprocessors“,IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), Atlanta, GA, Oct 2008
S. Pasricha, N. Dutt, “A Framework for Co-synthesis of Memory and Communication Architectures for MPSoC“, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 3, pp. 408-420, Mar 2007
S. Pasricha, N. Dutt, “COSMECA: Application Specific Co-Synthesis of Memory and Communication Architectures for MPSoC“, IEEE/ACM Design Automation and Test in Europe Conference (DATE), Munich, Germany, Mar 2006