Reliable and Energy-Efficient HW/SW Codesign for Manycore Processors

With increasing core counts ushering in power-constrained multiprocessor system-on-chips (MPSoCs), optimizing power dissipated by the computation cores and the network-on-chip (NoC) fabric is critical. At the same time, with increased power densities, especially in 3D ICs, problems of IR drops in the Power Delivery Network (PDN) as well as thermal hot spots on the die are very severe. Additionally, variations in emerging fabrication processes introduce significant unpredictability in system behavior. System-level design approaches that are aware of these challenges are crucial for designing efficient MPSoCs. This project recognizes that for each new configuration of computation core and communication mapping on an MPSoC, the corresponding inter-core communication patterns, 3D on-chip thermal profile, IR-drop distribution in the PDN, as well as impact of process variations on system performance can vary significantly.

The research objective of this project is to design a novel system-level co-synthesis framework that intelligently maps computation and communication resources on a die to minimize overall system power (including computation, communication and chip-cooling power) and optimize the PDN architecture; while meeting performance goals and satisfying thermal constraints. The project also considers emerging challenges for multicore computing at runtime, such as soft and hard errors, dim and dark silicon, and process/voltage/thermal (PVT) variations.

Selected Publications

S. Qi, S. Pasricha, R. Kim, “MOELA: A Multi-Objective Evolutionary/Learning Design Space Exploration Framework for 3D Heterogeneous Manycore Platforms”, IEEE/ACM DATE, 2023.

K. Khan, S. Pasricha, “A Reinforcement Learning Framework with Region-Awareness and Shared Path Experience for Efficient Routing in Networks-on-Chip”, IEEE Design & Test, 2023.

K. Khan, S. Pasricha and R. Kim, “RACE: A Reinforcement Learning Framework for Improved Adaptive Control of NoC Channel Buffers”, ACM GLSVLSI, 2022. (Best Paper Award Candidate)

Y. Raparti, S. Pasricha, “PARM: Power Supply Noise Aware Resource Management for NoC based Multicore Systems in the Dark Silicon Era,” IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 2018.

N. Kapadia, S. Pasricha, “A Runtime Framework for Robust Application Scheduling with Adaptive Parallelism in the Dark-Silicon Era”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 25, No. 2, pp. 534-546, Feb. 2017. 

Y. Raparti, N. Kapadia, S. Pasricha, “ARTEMIS: An Aging-Aware Runtime Application Mapping Framework for 3D NoC-based Chip Multiprocessors”, IEEE Transactions on Multi-Scale Computing Systems (TMSCS), Vol. 3, No. 2, pp. 72-85, Apr-Jun 2017. (Selected as Featured Paper for Apr-Jun 2017 issue)

S. Maiti, S. Pasricha, “DELCA: DVFS Efficient Low Cost Multicore Architecture,” ACM Great Lakes Symposium on VLSI (GLSVLSI) , May 2017.

V. Y. Raparti, S. Pasricha, “CHARM: A Checkpoint-based Resource Management Framework for Reliable Multicore Computing in the Dark Silicon Era,” IEEE International Conference on Computer Design (ICCD), Oct 2016.

V. Y. Raparti, S. Pasricha, “A Cross-Layer Runtime Framework for Checkpoint-based Soft-Error and Aging Management in SoCs,” SRC Techcon, Sep 2016.

N. Kapadia, S. Pasricha, “A System-Level Co-Synthesis Framework for Power Delivery and On-chip Data Networks in Application-Specific 3D ICs”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol.24, no.1, pp.3-16, Jan. 2016.

N. Kapadia, V. Y. Raparti, S. Pasricha, “ARTEMIS: An Aging-Aware Run-Time Application Mapping Framework for 3D NoC based Chip Multiprocessors,” IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2015. 

S. Maiti, N. Kapadia, S. Pasricha, “Process Variation Aware Dynamic Power Management in Multicore Systems with Extended Range Voltage/Frequency Scaling,” IEEE MWSCAS 2015. 

N. Kapadia, S. Pasricha, “A Framework for Low Power Synthesis of Interconnection Networks-on-Chip with Multiple Voltage Islands “,  Integration, the VLSI Journal, 45(3):271-281, Jun 2012.