Cross-Layer Design of Networks-on-Chip (NoCs)

Shrinking feature sizes and the increasing proliferation of mixed-signal and 3D integration are elevating rates of faults, variation, and aging related degradation in integrated circuits, threatening the reliability of communication between cores in system-on-chip (SoC) architectures. It is well known that performance for most SoCs today is interconnect-limited and the design of a high performance network-on-chip (NoC) will become a crucial step as core counts increase from tens today to hundreds in the near future, and 3D die stacking becomes the norm. But the NoC is a key component for another reason: it constitutes a single point of failure on a chip. Mechanisms for fault detection and recovery are thus vital for NoCs, especially in 3D ICs where greater thermal stress due to higher temperatures and thermal cycling accelerates a multitude of degradation affects, increasing transient and permanent fault rates at runtime. Unfortunately, current techniques to ensure NoC reliability at runtime, including fault tolerant routing, and architectural solutions operate at only one level of the system stack. Such single-layer techniques possess limited knowledge of application execution activity, and are therefore reactive in behavior, making worst-case assumptions about other layers. As a result, they introduce significant power, area, and performance overheads during typical-case operation for corner-case errors that occur very infrequently.

The research objective of this project is to realize a multi-objective computer-aided design (CAD) automation framework at the system-level, where design decisions have the most impact, to assist chip designers trade-off reliability with competing design constraints within tight time-to-market constraints. The research aims to create novel tools and techniques that will have a significant impact in industry by improving designer productivity and ushering in new levels of cost-efficiency during the reliable-by-construction design of network fabrics for SoCs. The project also exploits paradigms of approximate computing, security, and innovative architectures to push the state-of-the-art in NoC design.

Selected Publications

V. Y. Raparti, S. Pasricha, “Approximate NoC and Memory Controller Architectures for GPGPU Accelerators, IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol. 31, Iss 5., May 2020.

Y. Raparti, S. Pasricha, “Lightweight Mitigation of Hardware Trojan Attacks in NoC-based Manycore Computing,” IEEE/ACM Design Automation Conference (DAC), Las Vegas, NV, USA, Jun. 2019

Y. Raparti, S. Pasricha, “DAPPER: Data Aware Approximate NoC for GPGPU Architectures,” IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Torino, Italy, Oct 2018. (Best Paper Award)

V. Y. Raparti, S. Pasricha, “RAPID: Memory-Aware NoC for Latency Optimized GPGPU Architectures“, IEEE Transactions on Multi-Scale Computing Systems (IEEE TMSCS), Vol. 4, No. 4, Oct-Dec 2018. 

Y. Raparti, S. Pasricha, “PARM: Power Supply Noise Aware Resource Management for NoC based Multicore Systems in the Dark Silicon Era,” IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 2018.

V. Y. Raparti, S. Pasricha, “Memory-Aware Circuit Overlay NoCs for Latency Optimized GPGPU Architectures,” IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2016.

P. Pande, S. Pasricha, H, Matsutani, “The Future of NoCs: New Technologies and Architectures,” IEEE International Conference on VLSI Design (VLSID), Jan 2016.

Y. Zou, S. Pasricha, “HEFT: A Hybrid System-Level Framework for Enabling Energy-Efficient Fault-Tolerance in NoC based MPSoCs,” ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct 2014.

T. Pimpalkhute, S. Pasricha, “An Application-Aware Heterogeneous Prioritization Framework for NoC based Chip Multiprocessors”, IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2014. 

T. Pimpalkhute, S. Pasricha, “NoC Scheduling for Improved Application-Aware and Memory-Aware Transfers in Multi-Core Systems”, IEEE International Conference on VLSI Design (VLSID), Jan. 2014. 

N. Kapadia, S. Pasricha, “A Co-Synthesis Methodology for Power Delivery and Data Interconnection Networks in 3D ICs”, IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2013. 

M. Salas, S. Pasricha, “The Roce-Bush Router: A Case for Routing-centric Dimensional Decomposition for Low-latency 3D NoC Routers”, ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct 2012. 

Y. Zou, Y. Xiang, S. Pasricha, “Analysis of On-chip Interconnection Network Interface Reliability in Multicore Systems”, IEEE International Conference on Computer Design (ICCD), Oct. 2011.

S. Pasricha, Y. Zou, “A Low Overhead Fault Tolerant Routing Scheme for 3D Networks-on-Chip“, IEEE International Symposium on Quality Electronic Design (ISQED) , Santa Clara, CA, Mar 2011 

S. Kwon, S. Pasricha, “POSEIDON: A Framework for Application-Specific Network-on-Chip Synthesis for Heterogeneous Chip Multiprocessors“, IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, Mar 2011

S. Pasricha, Y. Zou, “NS-FTR: A Fault Tolerant Routing Scheme for Networks on Chip with Permanent and Runtime Intermittent Faults“, IEEE/ACM Asia & South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, Jan 2011

Y. Zou, S. Pasricha, “NARCO: Neighbor Aware Turn Model Based Fault Tolerant Routing for NoCs“,  IEEE Embedded System Letters, Vol. 2, No. 3, Sep 2010.

S. Pasricha, Y. Zou, D. Connors, H. J. Siegel, “OE+IOE: A Novel Turn Model Based Fault Tolerant Routing Scheme for Networks-on-Chip“, Proc. IEEE/ACM  International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS),Scottsdale, AZ, Oct 2010

S. Pasricha, “Exploring Serial Vertical Interconnects for 3D ICs“, IEEE/ACM Design Automation Conference (DAC 2009), San Francisco, CA, Jul 2009

A. Gupta, S. Pasricha, N. Dutt, F. Kurdahi, K. Khouri, M. Abadir, “On-Chip Communication Architecture Based Thermal Management for SoCs“, IEEE VLSI Design, Automation & Test (VLSI-DAT), Hsinchu, Taiwan, Apr 2009 

S. Pasricha, N. Dutt, F. Kurdahi, “Dynamically Reconfigurable On-Chip Communication Architectures for Multi Use-Case Chip Multiprocessor Applications“, IEEE/ACM Asia & South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, Jan 2009

S. Pasricha, F. Kurdahi, N. Dutt, “Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications“, IEEE VLSI Design Conference (VLSID), New Delhi, India, Jan 2009

S. Pasricha, Y. Park, S. Pasricha, Y. Park, F. Kurdahi, N. Dutt, “Incorporating PVT Variations in System-level Power Exploration of On-Chip Communication Architectures”, IEEE VLSI Design Conference (VLSID), Bangalore, IndiaJan 2008

S. Pasricha, Y. Park, F. Kurdahi, N. Dutt, “System-Level Power-Performance Trade-Offs in Bus Matrix Communication Architecture Synthesis”, IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)Seoul, KoreaOct 2006

S. Pasricha, N. Dutt,  M. Ben-Romdhane, “Constraint-Driven Bus Matrix Synthesis for MPSoC“, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, Jan 2006 (Best Paper Award)