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application/pdfIEEEIEEE Transactions on Multi-Scale Computing Systems;2018;4;4;10.1109/TMSCS.2018.2871094GPGPUmemory controlleron-chip interconnection networksoverlay circuitsRAPID: Memory-Aware NoC for Latency Optimized GPGPU ArchitecturesVenkata Yaswanth RapartiSudeep Pasricha
IEEE Transactions on Multi-Scale Computing Systems8741 Oct.-Dec. 20184410.1109/TMSCS.2018.2871094887
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