The EPIC Lab’s research in hardware security spans electronic, wireless, and photonic computing platforms, with a particular emphasis on safeguarding emerging architectures against an increasingly sophisticated threat landscape. Our proposed works introduce novel security frameworks for optical neural network accelerators, chiplet-based systems, and manycore architectures, addressing vulnerabilities ranging from denial‑of‑service attacks to hardware Trojans and covert snooping channels. The lab has pioneered techniques that exploit inherent device‑level characteristics—such as process variations in photonic components—to build lightweight, intrinsic defenses, while also developing secure routing, detection, and mitigation strategies for Network‑on‑Chip (NoC) and chiplet interconnects. Complementing these contributions, EPIC lab researchers have articulated broader reliability, security, and sustainability challenges in modern memory and interconnect technologies, helping shape the design of resilient next‑generation computing systems. Collectively, this body of work advances a holistic vision for secure, trustworthy, and high‑performance hardware platforms across heterogeneous computing domains.
Selected Publications
S. Afifi, I. Thakkar, S. Pasricha, “SafeLight: Enhancing Security in Optical Convolutional Neural Network Accelerators”, IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, Mar 2025.
B. Ray, S. Raghunathan, S. Pasricha, “Reliability, Security and Sustainability Challenges in 3D NAND Flash SSDs”, IEEE Design & Test, 2025.
E. Taheri, P. Aghanoury, S. Pasricha, M. Nikdast, N. Sehatbakhsh, “SCRIPT: A Multiobjective Routing Framework for Securing Chiplet Systems against DoS Attacks”, ACM Great Lakes Symposium on VLSI (GLSVLSI), 2024
S. Pasricha, J. Jose, S. Deb, “Electronic, Wireless, and Photonic Network-on-Chip Security: Challenges and Countermeasures”, Vol. 39, Iss. 6, pp. 90-98, IEEE Design & Test, Dec 2022.
S. V. R. Chittamuru, I. Thakkar, S. Pasricha, S. S. Vatsavai, and V. Bhat, “Exploiting Process Variations to Secure Photonic NoC Architectures from Snooping Attacks”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (TCAD), Volume: 40, Issue: 5, May 2021.
Y. Raparti, S. Pasricha, “Lightweight Mitigation of Hardware Trojan Attacks in NoC-based Manycore Computing,” IEEE/ACM Design Automation Conference (DAC), Las Vegas, NV, USA, Jun. 2019
S. V. R. Chittamuru, I. Thakkar, S. Pasricha, “SOTERIA: Exploiting Process Variations to Enhance Hardware Security with Photonic NoC Architectures,” IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 2018.
S. Pasricha, S. V. R. Chittamuru, I. Thakkar, V. Bhat, “Securing Photonic NoC Architectures from Hardware Trojans”, IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Torino, Italy, Oct 2018.