The EPIC Lab’s research on reliable and energy‑efficient hardware/software co‑design for manycore processors develops cross‑layer frameworks that intelligently manage performance, power, and reliability in deeply scaled and increasingly heterogeneous computing platforms. This work introduces multi‑objective design‑space exploration techniques for 3D manycore systems, power‑supply‑noise‑aware and thermal‑aware resource management, and adaptive runtime scheduling frameworks that respond to process variation, aging, and soft‑error vulnerabilities. The lab has advanced DVFS‑efficient multicore architectures, checkpoint‑based reliability management, and aging‑aware application mapping strategies that maintain system robustness in the dark‑silicon era. Complementary contributions include co‑synthesis of power‑delivery and interconnect networks, variation‑aware workload mapping, and hybrid fault‑tolerance mechanisms that balance energy efficiency with dependable operation. Collectively, this research establishes a comprehensive HW/SW co‑design methodology that enables scalable, resilient, and energy‑optimized manycore processors capable of sustaining high performance under real‑world constraints.
Selected Publications
S. Qi, S. Pasricha, R. Kim, “MOELA: A Multi-Objective Evolutionary/Learning Design Space Exploration Framework for 3D Heterogeneous Manycore Platforms”, IEEE/ACM DATE, 2023.
Y. Raparti, S. Pasricha, “PARM: Power Supply Noise Aware Resource Management for NoC based Multicore Systems in the Dark Silicon Era,” IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 2018.
Y. Raparti, N. Kapadia, S. Pasricha, “ARTEMIS: An Aging-Aware Runtime Application Mapping Framework for 3D NoC-based Chip Multiprocessors”, IEEE Transactions on Multi-Scale Computing Systems (TMSCS), Vol. 3, No. 2, pp. 72-85, Apr-Jun 2017. (Selected as Featured Paper for Apr-Jun 2017 issue)
S. Maiti, S. Pasricha, “DELCA: DVFS Efficient Low Cost Multicore Architecture,” ACM Great Lakes Symposium on VLSI (GLSVLSI) , May 2017.
N. Kapadia, S. Pasricha, “A Runtime Framework for Robust Application Scheduling with Adaptive Parallelism in the Dark-Silicon Era”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 25, No. 2, pp. 534-546, Feb. 2017.
V. Y. Raparti, S. Pasricha, “CHARM: A Checkpoint-based Resource Management Framework for Reliable Multicore Computing in the Dark Silicon Era,” IEEE International Conference on Computer Design (ICCD), Oct 2016.
N. Kapadia, S. Pasricha, “A System-Level Co-Synthesis Framework for Power Delivery and On-chip Data Networks in Application-Specific 3D ICs”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol.24, no.1, pp.3-16, Jan. 2016.
V. Y. Raparti, S. Pasricha, “A Cross-Layer Runtime Framework for Checkpoint-based Soft-Error and Aging Management in SoCs,” SRC Techcon, Sep 2016.
N. Kapadia, V. Y. Raparti, S. Pasricha, “ARTEMIS: An Aging-Aware Run-Time Application Mapping Framework for 3D NoC based Chip Multiprocessors,” IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2015.
S. Maiti, N. Kapadia, S. Pasricha, “Process Variation Aware Dynamic Power Management in Multicore Systems with Extended Range Voltage/Frequency Scaling,” IEEE MWSCAS 2015.
N. Kapadia, S. Pasricha, “Process-Variation and Soft-Error Reliability-Aware Workload Mapping with Adaptive Parallelism in SoCs ,” SRC Techcon, 2015.
N. Kapadia, S. Pasricha, “VARSHA: Variation and Reliability-Aware Application Scheduling with Adaptive Parallelism in the Dark-Silicon Era,” IEEE/ACM Design Automation & Test in Europe (DATE), Mar 2015.
N. Kapadia, S. Pasricha, “PRATHAM: A Power Delivery-Aware and Thermal-Aware Mapping Framework for Parallel Embedded Applications on 3D MPSoCs,” IEEE International Conference on Computer Design (ICCD), Oct 2014
N. Kapadia, S. Pasricha, “Process Variation Aware Synthesis of Application-Specific MPSoCs to Maximize Yield”, IEEE International Conference on VLSI Design (VLSID), Jan. 2014.
Y. Zou, S. Pasricha, “HEFT: A Hybrid System-Level Framework for Enabling Energy-Efficient Fault-Tolerance in NoC based MPSoCs,” ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct 2014.
N. Kapadia, S. Pasricha, “A Co-Synthesis Methodology for Power Delivery and Data Interconnection Networks in 3D ICs”, IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2013.
N. Kapadia, S. Pasricha, “A Framework for Low Power Synthesis of Interconnection Networks-on-Chip with Multiple Voltage Islands “, Integration, the VLSI Journal, 45(3):271-281, Jun 2012.