The EPIC Lab’s research on cross‑layer Networks‑on‑Chip (NoCs) advances the design of intelligent, reliable, and energy‑efficient on‑chip communication fabrics for heterogeneous multicore and manycore systems. This work spans more than a decade of innovations across application‑aware routing, power‑ and variation‑aware synthesis, fault‑tolerant communication, and emerging interconnect technologies for 2D, 3D, and chiplet‑based platforms. The lab has pioneered reinforcement‑learning‑driven NoC control frameworks, multi‑objective design‑space exploration for heterogeneous architectures, and approximate NoC designs tailored for GPGPU workloads. Complementary contributions address reliability and security challenges—including hardware Trojan mitigation, power‑supply‑noise‑aware resource management, and deadlock‑free, fault‑tolerant routing for chiplet systems. EPIC lab researchers have also explored forward‑looking interconnect paradigms such as optical, wireless, and DNA‑scale communication, highlighting the architectural implications of future technologies. Collectively, this research establishes a comprehensive cross‑layer methodology that integrates device‑level constraints, circuit‑level robustness, architecture‑level optimization, and application‑level behavior to enable scalable, resilient, and high‑performance NoC‑based computing platforms.
Selected Publications
K. Khan, S. Pasricha, “CAFEEN: A Cooperative Approach for Energy Efficient NoCs with Multi-Agent Reinforcement Learning”, IEEE Design & Test, 2024.
K. Khan, S. Pasricha, “A Reinforcement Learning Framework with Region-Awareness and Shared Path Experience for Efficient Routing in Networks-on-Chip”, IEEE Design & Test, 2023
S. Qi, S. Pasricha, R. Kim, “MOELA: A Multi-Objective Evolutionary/Learning Design Space Exploration Framework for 3D Heterogeneous Manycore Platforms”, IEEE/ACM DATE, 2023.
A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, “Interconnects for DNA, Quantum, In-Memory and Optical Computing: Insights from a Panel Discussion”, IEEE Micro, Volume: 42, Issue: 3, 01 May-June 2022.
E. Taheri, M. Nikdast, S. Pasricha, “DeFT: A Deadlock-Free and Fault-Tolerant Routing Algorithm for 2.5D Chiplet Systems”, IEEE/ACM Design, Automation and Test in Europe (DATE) Conference and Exhibition, Mar 2022.
K. Khan, S. Pasricha and R. Kim, “RACE: A Reinforcement Learning Framework for Improved Adaptive Control of NoC Channel Buffers”, ACM GLSVLSI, 2022. (Best Paper Award Candidate)
V. Y. Raparti, S. Pasricha, “Approximate NoC and Memory Controller Architectures for GPGPU Accelerators“, IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol. 31, Iss 5., May 2020.
Y. Raparti, S. Pasricha, “Lightweight Mitigation of Hardware Trojan Attacks in NoC-based Manycore Computing,” IEEE/ACM Design Automation Conference (DAC), Las Vegas, NV, USA, Jun. 2019
Y. Raparti, S. Pasricha, “DAPPER: Data Aware Approximate NoC for GPGPU Architectures,” IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Torino, Italy, Oct 2018. (Best Paper Award)
V. Y. Raparti, S. Pasricha, “RAPID: Memory-Aware NoC for Latency Optimized GPGPU Architectures“, IEEE Transactions on Multi-Scale Computing Systems (IEEE TMSCS), Vol. 4, No. 4, Oct-Dec 2018.
Y. Raparti, S. Pasricha, “PARM: Power Supply Noise Aware Resource Management for NoC based Multicore Systems in the Dark Silicon Era,” IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 2018.
V. Y. Raparti, S. Pasricha, “Memory-Aware Circuit Overlay NoCs for Latency Optimized GPGPU Architectures,” IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2016.
P. Pande, S. Pasricha, H, Matsutani, “The Future of NoCs: New Technologies and Architectures“, IEEE International Conference on VLSI Design (VLSID), Jan 2016.
Y. Zou, S. Pasricha, “HEFT: A Hybrid System-Level Framework for Enabling Energy-Efficient Fault-Tolerance in NoC based MPSoCs,” ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct 2014
T. Pimpalkhute, S. Pasricha, “An Application-Aware Heterogeneous Prioritization Framework for NoC based Chip Multiprocessors”, IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2014
T. Pimpalkhute, S. Pasricha, “NoC Scheduling for Improved Application-Aware and Memory-Aware Transfers in Multi-Core Systems”, IEEE International Conference on VLSI Design (VLSID), Jan. 2014.
N. Kapadia, S. Pasricha, “VERVE: A Framework for Variation-Aware Energy Efficient Synthesis of NoC-based MPSoCs with Voltage Islands”, IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2013.
N. Kapadia, S. Pasricha, “A Co-Synthesis Methodology for Power Delivery and Data Interconnection Networks in 3D ICs”, IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2013.
Y. Zou, S. Pasricha, “Reliability-Aware and Energy-Efficient Synthesis of NoC based MPSoCs”, IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2013.
N. Kapadia, S. Pasricha, “A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands”, IEEE International Conference on VLSI Design (VLSID), Jan. 2012.
M. Salas, S. Pasricha, “The Roce-Bush Router: A Case for Routing-centric Dimensional Decomposition for Low-latency 3D NoC Routers”, ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct 2012.
Y. Zou, Y. Xiang, S. Pasricha, “Analysis of On-chip Interconnection Network Interface Reliability in Multicore Systems”, IEEE International Conference on Computer Design (ICCD), Oct. 2011.
N. Kapadia, S. Pasricha, “VISION: A Framework for Voltage Island Aware Synthesis of Interconnection Networks-on-Chip”, ACM Great Lakes Symposium on VLSI (GLSVLSI), Lausanne, Switzerland, May 2011.
S. Pasricha, Y. Zou, “A Low Overhead Fault Tolerant Routing Scheme for 3D Networks-on-Chip“, IEEE International Symposium on Quality Electronic Design (ISQED) , Santa Clara, CA, Mar 2011
S. Kwon, S. Pasricha, “POSEIDON: A Framework for Application-Specific Network-on-Chip Synthesis for Heterogeneous Chip Multiprocessors“, IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, Mar 2011
S. Pasricha, Y. Zou, “NS-FTR: A Fault Tolerant Routing Scheme for Networks on Chip with Permanent and Runtime Intermittent Faults“, IEEE/ACM Asia & South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, Jan 2011
Y. Zou, S. Pasricha, “NARCO: Neighbor Aware Turn Model Based Fault Tolerant Routing for NoCs“, IEEE Embedded System Letters, Vol. 2, No. 3, Sep 2010.
S. Pasricha, Y. Zou, D. Connors, H. J. Siegel, “OE+IOE: A Novel Turn Model Based Fault Tolerant Routing Scheme for Networks-on-Chip“, Proc. IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS),Scottsdale, AZ, Oct 2010
S. Pasricha, “Exploring Serial Vertical Interconnects for 3D ICs“, IEEE/ACM Design Automation Conference (DAC 2009), San Francisco, CA, Jul 2009
A. Gupta, S. Pasricha, N. Dutt, F. Kurdahi, K. Khouri, M. Abadir, “On-Chip Communication Architecture Based Thermal Management for SoCs“, IEEE VLSI Design, Automation & Test (VLSI-DAT), Hsinchu, Taiwan, Apr 2009
S. Pasricha, N. Dutt, F. Kurdahi, “Dynamically Reconfigurable On-Chip Communication Architectures for Multi Use-Case Chip Multiprocessor Applications“, IEEE/ACM Asia & South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, Jan 2009
S. Pasricha, F. Kurdahi, N. Dutt, “Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications“, IEEE VLSI Design Conference (VLSID), New Delhi, India, Jan 2009
S. Pasricha, Y. Park, S. Pasricha, Y. Park, F. Kurdahi, N. Dutt, “Incorporating PVT Variations in System-level Power Exploration of On-Chip Communication Architectures”, IEEE VLSI Design Conference (VLSID), Bangalore, India, Jan 2008
S. Pasricha, Y. Park, F. Kurdahi, N. Dutt, “System-Level Power-Performance Trade-Offs in Bus Matrix Communication Architecture Synthesis”, IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Seoul, Korea, Oct 2006
S. Pasricha, N. Dutt, M. Ben-Romdhane, “Constraint-Driven Bus Matrix Synthesis for MPSoC“, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, Jan 2006 (Best Paper Award)