Graduate Exam Abstract
Venkata Yaswanth RapartiPh.D. Final
July 30, 2019, 10:00 am - 12:00 pm
RELAX: Cross-layer Resource Management for Reliable NoC-based 2D and 3D Manycore Architectures
Abstract: Emerging 2D and 3D manycore processors are facing numerous challenges due to technology scaling that impact their reliability, power dissipation, performance, and security. With growing parallelism in applications and increasing core counts, traditional resource management frameworks and critical on-chip components such as networks-on-chip (NoC) and memory controllers (MCs) do not scale well to efficiently cope with this new and complex design space of manycore design. For example, phenomena such as BTI, HCI, and EM lead to permanent faults due to aging in manycore processors and NoC routers. Simultaneously, phenomena such as alpha particle strikes (soft errors), and power supply noise (PSN) lead to transient faults across components. Mechanisms to overcome these challenges require complex hardware architectures that are designed and integrated at various global locations. Unfortunately, such global fabrication of manycore processors makes them vulnerable to security threats due to hardware Trojans that may be inserted in third-party (3PIP) components such as NoCs. We address these issues by designing a cross-layer resource management framework called RELAX that enhances the performance, reliability, and security of NoC-based 2D and 3D manycore processors, while meeting a diverse set of platform constraints related to dark silicon power, fault tolerance, thermal, and real-time performance.
Adviser: Prof. Sudeep Pasricha
Non-ECE Member: Prof. Wim Bohm
Member 3: Prof. Anura Jayasumana
Addional Members: Prof. Ryan Kim
 N. Kapadia, V. Y. Raparti, S. Pasricha, “ARTEMIS: An Aging-Aware Runtime Application Mapping Framework for 3D NoC-based Chip Multiprocessors”, ACM, NOCS Sep. 2015.
 V. Y. Raparti, S. Pasricha, “Memory-Aware Circuit Overlay NoCs for Latency Optimized GPGPU Architectures,” IEEE, ISQED, Mar. 2016.
 V. Y. Raparti, S. Pasricha, “A Cross-Layer Runtime Framework for Checkpoint-based Soft-Error and Aging Management in SoCs,” SRC Techcon, Sep 2016.
 V. Y. Raparti, S. Pasricha, “CHARM: A Checkpoint-based Resource Management Framework for Reliable Multicore Computing in the Dark Silicon Era,” IEEE, ICCD, Oct. 2016.
 V. Y. Raparti, N. Kapadia, S. Pasricha, “ARTEMIS: An Aging-Aware Runtime Application Mapping Framework for 3D NoC-based Chip Multiprocessors”, IEEE, TMSCS, Apr-Jun. 2017. (Selected as Featured Paper for Apr-Jun 2017 issue)
 V. Y. Raparti, S. Pasricha, “PARM: Power Supply Noise Aware Resource Management for NoC based Multicore Systems in the Dark Silicon Era,” IEEE/ACM, DAC, Jun. 2018.
 V. Y. Raparti, S. Pasricha, “RELAX: Cross-Layer Resource Management for Reliable NoC-based 2D and 3D Manycore Architectures in the Dark Silicon Era”, ACM SIGDA DAC PhD. Forum, Jun. 2018
 V. Y. Raparti, S. Pasricha, “RAPID: Memory-Aware NoC for Latency Optimized GPGPU Architectures,” IEEE TMSCS, Oct. 2018.
 V. Y. Raparti, S. Pasricha, “DAPPER: Data Aware Approximate NoC for GPGPU Architectures,” IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Oct. 2018. (Best Paper Award)
V. Y. Raparti, S. Pasricha, “Lightweight Mitigation of Hardware Trojan Attacks in NoC-based Manycore Computing,” IEEE/ACM Design Automation Conference (DAC), Jun. 2019
V. Y. Raparti, S. Pasricha, “Approximate NoC and Memory Controller Architectures for GPGPU Accelerators,” IEEE TPDS, (Under review)
Program of Study: