Graduate Exam Abstract

Venkata Yaswanth Raparti

Ph.D. Preliminary
September 6, 2018, 2:30 pm - 4:00 pm
ECE conference room
RELAX: Cross-Layer Resource Management for Reliable NoC-based 2D and 3D Manycore Architectures in the Dark Silicon Era

Abstract: Emerging 2D and 3D chip multiprocessors (CMPs) are facing numerous challenges due to technology scaling that impact their reliability, power dissipation, and performance. With growing application parallelism and the increasing core counts, traditional application schedulers and resource management frameworks do not scale well to efficiently traverse this new and complex CMP design space. For instance, phenomena such as BTI and EM lead to permanent faults due to aging in CMP cores and NoC routers. Simultaneously, alpha particle strikes (soft errors) and power supply noise (PSN) impacts lead to transient faults in components. Mechanisms to overcome these challenges incur large overheads in power and performance. We address these issues by designing a cross-layer resource management framework (called RELAX) that enhances performance of NoC based 2D and 3D CMPs, while meeting a diverse set of platform constraints (e.g., dark silicon power, fault tolerance, thermal).

Adviser: Sudeep Pasricha
Co-Adviser: NA
Non-ECE Member: Wim Bohm
Member 3: Anura Jayasumana
Addional Members: Ryan Kim

[1] V. Y. Raparti, N. Kapadia, S. Pasricha, “ARTEMIS: An Aging-Aware Runtime Application Mapping Framework for 3D NoC-based Chip Multiprocessors”, IEEE, TMSCS, Apr-Jun 2017. (Selected as Featured Paper for Apr-Jun 2017 issue)
[2] V. Y. Raparti, S. Pasricha, “CHARM: A Checkpoint-based Resource Management Framework for Reliable Multicore Computing in the Dark Silicon Era,” IEEE, ICCD, Oct 2016.
[3] V. Y. Raparti, S. Pasricha, “A Cross-Layer Runtime Framework for Checkpoint-based Soft-Error and Aging Management in SoCs,” SRC Techcon, Sep 2016.
[4] V. Y. Raparti, S. Pasricha, “PARM: Power Supply Noise Aware Resource Management for NoC based Multicore Systems in the Dark Silicon Era,” to appear, IEEE/ACM, DAC, Jun. 2018.
[5] V. Y. Raparti, S. Pasricha, “Memory-Aware Circuit Overlay NoCs for Latency Optimized GPGPU Architectures,” IEEE, ISQED, Mar. 2016.
[6] V. Y. Raparti, S. Pasricha, “RAPID: Memory-Aware NoC for Latency Optimized GPGPU Architectures,” IEEE TMSCS, 2016, under review
[7] Y. Raparti, S. Pasricha, “DAPPER: Data Aware Approximate NoC for GPGPU Architectures,” to appear, IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Torino, Italy, Oct 2018.

Program of Study:
ECE 561
ECE 554
ECE 514
CS 420
CS 545
ECE 658
ECE 661
ECE 520