Abstract: With the increase of scaling, the problem of soft errors in control logic has become a great concern for logic designers. In this paper we will show a new method that will provide the accuracy that we feel is necessary to report the FIT for each node and also limit amount of run-time. This method will use a pre-characterization of gates to limit the run-time while not hurting the accuracy.
Adviser: Tom Chen Co-Adviser: Non-ECE Member: Yashwant K. Malaiya, Computer Science Member 3: Bill Eads, ECE Addional Members: