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Graduate Exam Abstract


Shirish Bahirat

Ph.D. Final

March 28, 2014, 3:00 to 5:00 PM

ECE Conference Room (C101B)

Design and Synthesis of Hybrid Nanophotonic Network-On-Chip Architectures


Abstract: Networks on Chip (NoCs) have emerged as scalable communication fabrics that can support high bandwidths massively parallel multi-core systems. However, traditional electrical NoC implementations still need to overcome the challenges of high data transfer latencies and large power consumption. On-chip photonic interconnects with high performance-per-watt characteristics have recently been proposed as an alternative to address these challenges for intra- chip communication. However, with increasing embedded application complexity, hardware dependencies, and performance variability, optimizing hybrid nanophotonic-electric NoCs requires traversing a massive design space. No prior work has addressed this problem to the best of our knowledge. We present the first effort in this direction for design and synthesis of hybrid nanophotonic network-on-chip architectures.

Adviser: Dr. Sudeep Pasricha
Co-Adviser: N/A
Non-ECE Member: Dr. Wim Bohm
Member 3: Dr. T. W. Chen, Dr. H.J. Siegel
Addional Members: N/A

Publications:
Conference Papers
C9: S. Bahirat and S. Pasricha, 3D-HELIX: Design and Synthesis of Hybrid Nanophotonic Application-Specific 3D Network-On-Chip Architectures, (invited paper) High-Performance and Embedded Architectures and Compilers, (HiPEAC) Jan. 2014
C8: S. Bahirat and S. Pasricha, HELIX: Design and Synthesis of Hybrid Nanophotonic Application-Specific Network-On-Chip Architectures, To appear, IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2014.
C7: S. Bahirat, Design and Synthesis of Hybrid Nanophotonic NoCs for Future Many-Core Architectures, DAC PhD Forum 2013
C6: S. Bahirat and S. Pasricha: A Particle Swarm Optimization approach for synthesizing application-specific hybrid photonic networks-on-chip. ISQED 2012 78-83
C5: J. Apodaca, B. Young, Luis Diego Briceno, J. Smith, S. Pasricha, A. Maciejewski, H. Siegel, S. Bahirat, B. Khemka, A. Ramirez, Y/ Zou: Stochastically robust static resource allocation for energy minimization with a makespan constraint in a heterogeneous computing environment. AICCSA 2011: 22-31 (Best paper award)
C4: S. Bahirat and S. Pasricha: OPAL: A multi-layer hybrid photonic NoC for 3D ICs. ASP-DAC 2011: 345-350
C3: B. Young, J. Apodaca, L. Briceno, J. Smith, S. Pasricha, A. Maciejewski, H. Siegel, B. Khemka, S. Bahirat, A. Ramirez, Y. Zou: Energy-Constrained Dynamic Resource Allocation in a Heterogeneous Computing Environment. ICPP Workshops 2011: 298-307
C2: S. Bahirat and S. Pasricha: UC-PHOTON: A novel hybrid photonic network-on-chip for multiple use-case applications. ISQED 2010: 721-729 (Best paper award)
C1: S. Bahirat and S. Pasricha: Exploring hybrid photonic networks-on-chip for emerging chip multiprocessors. CODES+ISSS 2009: 129-136

Journal Papers:
J2: S. Bahirat and S. Pasricha, METEOR: Hybrid Photonic Ring-Mesh Network-on-Chip for Multicore Architectures, accepted for publication, IEEE Transactions on Embedded Computing Systems (TECS), 2013.
J1: S. Bahirat and S. Pasricha, A Framework for Application-specific Hybrid Photonic Network-on-Chip Synthesis, under review for Integration, the VLSI Journal 2013

Posters:
P2: S. Bahirat and S. Pasricha: Design and Synthesis of Hybrid Nanophotonic NoCs for Future Many-Core Architectures, DAC PhD Forum 2013
P1: S. Bahirat and S. Pasricha: Hybrid Nano-photonic-electric On-chip Communication Architecture, CANDE Workshop 2009

Book
Design and Analysis of Disc Drive Servo Mechanical Subsystem Advanced Control System Design Application VDM Verlag (April 24, 2009), ISBN: 3639142128.


Program of Study:
ECE 670C
ECE 658
ECE 561
CS 575
ECE 795
ECE 795
NA
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