Graduate Exam Abstract
Ebad Taheri
Ph.D. Final
May 3, 2024, 10:00 am - 12:00 pm
LSC-306
Design and Optimization of Efficient, Fault-Tolerant and Secure 2.5D Chiplet Systems
Abstract: In response to the burgeoning demand for high-performance computing systems, this Ph.D. dissertation investigates the pivotal challenges surrounding Networks-on-Chip (NoCs) within the framework of 2.5D and 3D integration technologies, with a primary objective of enhancing the efficiency, fault tolerance, and security of forthcoming computing system architectures. The inherent limitations in bandwidth and reliability at the boundary of 2.5D chiplet systems engender significant challenges in traffic management, latency, and energy efficiency. Furthermore, the interconnected global network on an interposer, linking multiple chiplets, necessitates high-bandwidth, low-latency communication to accommodate the substantial traffic generated by numerous cores across diverse chiplets. This Ph.D. dissertation emphasizes various design aspects of NoCs, such as latency, energy efficiency, fault tolerance, and security. It explores the design of 3D NoCs leveraging Through-Silicon Vias (TSVs) for vertical communication. To address reliability concerns and fabrication costs associated with high TSV density, Partially Connected 3D NoC (PC-3DNoC) has been proposed. An adaptive congestion-aware TSV link selection algorithm is introduced to manage traffic load and optimize communication, resulting in reduced latency and improved energy efficiency. For 2.5D chiplet systems, a novel deadlock-free and fault-tolerant routing algorithm is presented. The fault-tolerant algorithm enhances redundancy in vertical link selection and offers improved network reachability with reduced latency compared to existing solutions, even in the presence of faults. Furthermore, to address the energy consumption concerns of silicon-photonic-based 2.5D networks, a reconfigurable power-efficient and congestion-aware silicon-photonic-based 2.5D Interposer network is proposed. The proposed photonic interposer utilizes phase change materials (PCMs) for dynamic reconfiguration and power gating of the photonic network, leading to lower latency and improved energy efficiency. Additionally, the research investigates the integration of optical computation and communication into 2.5D chiplet platforms for domain-specific machine learning (ML) processing. This approach aims to overcome limitations in computation density and communication speeds faced by traditional accelerators, paving the way for sustainable and scalable ML hardware. Furthermore, this dissertation proposes a 2.5D chiplet-based architecture utilizing a silicon-photonic-based interposer, which tackles the limitations of conventional bus-based communication by employing a novel switch-based network, achieving significant energy efficiency improvements for high-bandwidth, low-latency data movement in machine learning accelerators. The switch-based network employs our proposed optical switch based on Mach--Zehnder Interferometer (MZI) devices with a dividing state to facilitate broadcast and optimize communication for ML workloads. Finally, the dissertation explores security considerations in 2.5D chiplet systems with diverse, potentially untrusted chiplets. To address this, a secure routing framework for Network-on-Interposer is presented. The proposed secure framework protects the system against distributed denial-of-service (DDoS) attacks by concealing predictable routing paths. It leverages multi-objective optimization to balance efficiency and reliability for the NoI. The proposed contributions in this dissertation help advance the field of chip-scale interconnection networks by proposing novel techniques for improved performance, reliability, and power efficiency in 3D and 2.5D NoC architectures. These advancements hold promise for the design of future high-performance computing systems, particularly in the areas of machine learning and other computationally intensive applications.
Adviser: Prof. Mahdi Nikdast
Co-Adviser: Prof. Sudeep Pasricha
Non-ECE Member: Prof. Yashwant Malaiya, CS department
Member 3: Prof. Sudeep Pasricha
Addional Members: Prof. Anura Jayasumana, ECE
Publications:
1. E. Taheri, M. A. Mahdian, S. Pasricha, and M. Nikdast, "SwInt: A Non-Blocking Switch-
Based Silicon Photonic Interposer Network for 2.5D Machine Learning Accelerators", IEEE
Journal on Emerging and Selected Topics in Circuits and Systems (Submitted).
2. E. Taheri, S. Pasricha, and M. Nikdast, "ReD: A Reliable and Deadlock-Free Routing Al-
gorithm for 2.5D Chiplet Networks", IEEE Transactions on Computer-Aided Design of In-
tegrated Circuits and Systems (First revision submitted).
3. E. Taheri, P. aghanoury, S. Pasricha, M. Nikdast, and N. Sehatbakhsh, "SCRIPT: A Multi-
Objective Routing Framework for Securing Chiplet Systems against Distributed DoS At-
tacks", Proceedings of the Great Lakes Symposium on VLSI.
4. M. A. Mahdian, E. Taheri, K. Rahbardar Mojaver, and M. Nikdast, “Photonic Physically
Unclonable Functions using Ring-Assisted Contra-Directional Couplers”, IEEE/Optica Op-
tical Fiber Communication (OFC) Conference, 2024.
5. F Sunny, E. Taheri, M Nikdast, and S Pasricha, "Silicon Photonic 2.5 D Interposer Networks
for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Ac-
celerators", IEEE VLSI Test Symposium, 2024.
6. E. Taheri, M. A. Mahdian, S. Pasricha, and M. Nikdast, "TRINE: A Tree-Based Silicon
Photonic Interposer Network for Energy-Efficient 2.5 D Machine Learning Acceleration",
Proceedings of the 16th International Workshop on Network on Chip, 2023.
7. M. A. Mahdian, E. Taheri, S. Pasricha, and M. Nikdast, "Pars: A power-aware and reliable
control plane for silicon photonic switch fabrics", International Conference on Photonics in
Switching and Computing (PSC), 2023.
8. E. Taheri, R. G. Kim, and M. Nikdast, "AdEle+: An Adaptive Congestion-and-Energy-
Aware Elevator Selection for Partially Connected 3D Networks-on-Chip", IEEE Transac-
tions on Computers, 2023.
9. F Sunny, E. Taheri, M Nikdast, and S Pasricha, "Machine Learning Accelerators in 2.5
D Chiplet Platforms with Silicon Photonics", IEEE/ACM Design, Automation and Test in
Europe (DATE) Conference and Exhibition, 2023.
10. E. Taheri, S. Pasricha, and M. Nikdast, "ReSiPI: A Reconfigurable Silicon-Photonic 2.5D
Chiplet Network with PCMs for Energy-Efficient Interposer Communication", IEEE/ACM
International Conference on Computer-Aided Design (ICCAD), 2022.
11. E. Taheri, S. Pasricha, and M. Nikdast, "DeFT: A Deadlock-Free and Fault-Tolerant Routing
Algorithm for 2.5D Chiplet Systems", IEEE/ACM Design, Automation and Test in Europe
(DATE) Conference and Exhibition, 2022.
12. F. Sunny, E. Taheri, M. Nikdast, and S. Pasricha, “A Survey on Silicon Photonics for Deep
Learning,” ACM Journal on Emerging Technologies in Computing Systems (JETC) , 2021.
13. E. Taheri, R. G. Kim, and M. Nikdast, “AdEle: An Adaptive Congestion-and-Energy-Aware
Elevator Selection for Partially Connected 3D NoCs,” IEEE/ACM Design Automation Con-
ference (DAC), 2021.
14. A. Mirza, S. Manafi Avari, E. Taheri, S. Pasricha, and M. Nikdast, “Opportunities for Cross-
Layer Design in High-Performance Computing Systems with Integrated Silicon Photonic
Networks”, IEEE/ACM Design, Automation and Test in Europe (DATE) Conference and
Exhibition, 2020.
Program of Study:
GRAD 550
ECE 571
ECE 575
ECE 580B6
ECE 656
ECE 795
GRAD 544
GRAD 580A2
