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Anura Jayasumana

CNRL

Recent Publications by
Anura P. Jayasumana
COMPUTER NETWORKING RESEARCH LABORATORY

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    Books & Book Chapters

    • T. H. Illangasekare,  Q. Han, and A. P. Jayasumana, "Environmental Underground Sensing and Monitoring,"   Underground Sensing: Monitoring and Hazard Detection for Environment and Infrastructure, S. Pamukcu and L. Cheng (Editors), Academic Press,ISBN: 978-0-12-803139-1,     pp. 203-246, 2018
    • B. Albert and A. P. Jayasumana, FDDI and FDDI-II: Architecture, Protocols and Performance,Artech House, ISBN 0-89006-633-7, 430 pages, 1994.

 

       Recent Papers on Computer Networks (1995 - )

    • A. Gunathillake, A. V. Savkin and A. P. Jayasumana, "Robust Kalman Filter Based Decentralized Target Search and Prediction with Topology Maps," To appear in   IET Wireless Sensor Systems (pdf).

    • A. Gunathillake, A. V. Savkin and A. P. Jayasumana, "Topology Mapping Algorithm for 2D and 3D Wireless Sensor Networks Based on Maximum Likelihood Estimation," To appear in   Computer Networks,       https://doi.org/10.1016/j.comnet.2017.11.002
    • A. Gunathillake, M. Moradi, K. Thilakarathna, A. P.  Jayasumana and A. V. Savkin,  "Topology Maps for 3D Millimeter Wave Sensor Networks with Directional Antennas,"    Proc. 42nd IEEE Conference on Local Computer Networks (LCN 2017), Singapore, Oct. 2017.
    • N. Mosharraf, A. P. Jayasumana and Indrakshi Ray, "Using a History-Based Profile to Detect and Respond to DDoS Attacks," Proc. 14th International Conference on Security and Cryptography, Madrid, Spain, July 2017.
    • N. Mosharraf, A. P. Jayasumana and Indrakshi Ray, "A Distributed Mechanism to Protect against DDoS Attacks," Proc. 31st Annual IFIP WG 11.3 Conference on Data and Applications Security and Privacy (DBSec'17), Philadelphia, PA, USA, July  2017.
    • B. W. Hung, A. P. Jayasumana and V. W. Bandara, "INSiGHT: A System for Detecting Radicalization Trajectories in Large Heterogeneous Graphs," Proc. IEEE 2017 International Conference on Technologies for Homeland Security (HST2017), Waltham, Massachusetts, April 2017. (doi: 10.1109/THS.2017.7943441)(download)

    • A. F. Buoud and A. P. Jayasumana, "Topology Preserving Map to Physical Map - A Thin-Plate Spline Based Transform,"   Proc. 41st IEEE Conference on Local Computer Networks (LCN 2016), Dubai, UAE, Nov. 2016. (10.1109/LCN.2016.54)(download)
    • A. Gunathillake, A. Savkin and A. P. Jayasumana, "Maximum Likelihood Topology Maps for Wireless Sensor Networks Using an Automated Robot,"  Proc. 41st IEEE Conference on Local Computer Networks (LCN 2016), Dubai, UAE, Nov. 2016. (DOI: 10.1109/LCN.2016.62)(download)
    • N. Mosharraf and A. P. Jayasumana, "Packet-Pair Dispersion Signatures in Multihop Networks,"   Proc. 10th IEEE Workshop on Network Measurements (WNM2016),  LCN 2016, Dubai, UAE, Nov. 2016.


    Papers on VLSI & Testing (1995 - )

    • X. He, Y. K.  Malaiya, A. P. Jayasumana, K. P. Parker and S. Hird, "Principal Component Analysis-Based Compensation for Measurement Errors Due to Mechanical Misalignments in PCB Testing"  Proc. 41st International Test Conference (ITC'10), Austin, Texas, November 2010
    • A. P. Jayasumana, Y. K. Malaiya, X. He, K. P. Parker and S. Hird, "Compensation for Measurement Errors Due to Mechanical Misalignments in PCB Testing,"Presented at the IEEE 9th International Board Test Workshop (BTW'10), Fort Collins, CO, Sept. 2010.
    • X. He, Y. K.  Malaiya, A. P. Jayasumana, K. P. Parker and S. Hird, "An Outlier Detection Based Approach for PCB Testing,"  Proc. 40th International Test Conference (ITC09), Austin, Texas, November 2009. {Finalist for Best Paper Award}
    • X. He, Y. Malaiya, A. P. Jayasumana, K. P. Parker and S. Hird, "Outlier Detection in Capacitive Open Test Data Using Principal Component Analysis," Presented at the IEEE 8th International Board Test Workshop (BTW'09), Fort Collins, CO, Sept. 2009.

    • S. Wu, S. Jandhyala, Y. K. Malaiya and A. P. Jayasumana "Antirandom Testing: A Distance Based Approach,"  VLSI Design. Vol. 2008 (2008), Article ID 165709, 9 pages, doi:10.1155/2008/165709
    • A. Sharma, A.P. Jayasumana and Y. K. Malaiya, "X-IDDQ: A Novel Defect Detection Technique using IDDQ Data,''    Proc. 24th IEEE VLSI Test Symposium, Berkeley,  CA, April 2006.
    • A. S. Banthia, A. P. Jayasumana and Y.K. Malaiya, "Data Size Reduction for Clustering-Based Binning of ICs using Principal Component Analysis,"  Proc.  IEEE International Workshop on Defect Based Testing (DBT 2005),  CA, May 2005.
    • X. Jiang and A. P. Jayasumana, “Input Collapse of CMOS Logic Gates with a Series-Connected MOSFET Chain,” Proc. Seventh International Conference on Solid-State and Integrated-Circuit Technology (ICSICT2004), Beijing, China, October, 2004.
    • R. Turakhia, A. P. Jayasumana and Y. K. Malaiya, "Clustering-Based Production-Line Binning of ICs Based on IDDQ,'' Proc. IEEE International Workshop on Defect Based Testing (CDBT 2003), Nappa Valley, CA, pp. 65-73, April 2003

    • Xueping Jiang, A. P. Jayasumana, W. Zhang, S. Chiao, "A Proper Deep Submicron MOSFET Model (PDSMM) and Its Applications for Delay Modeling of CMOS Inverters,''   Proc. Sixth International Conference on Solid-State and Integrated-Circuit Technology (ICSICT2001), Shanghai, China,  Vol. 2, 875-878, October, 2001.
    • A. Rao, A.P. Jayasumana and Y.K. Malaiya, "Optimal Clustering and Statistical Identification of Defective ICs using IDDQ Testing,'' Proc.  IEEE International Workshop on Defect Based Testing (DBT 2000), Montreal, Canada, April 2000
    • S. Jandhyala, H. Balachandran, M. Sengupta and A. Jayasumana,  "Clustering Based Evaluation of IDDQ Measurements: Applications in Testing and Classification of ICs,'' Proc. IEEE VLSI Test Symposium, Montreal, Canada, pp. 444-449, April 2000.
    • S. Jandhyala, H. Balachandran, and A. Jayasumana, ``Reducing Dependence on Arbitrary Thresholds with IDDQ Testing,'' TI Technical Journal, Texas Instruments, Oct.- Dec. 1999
    • A. Palaniswami, A. Jayasumana and Y. K. Malaiya, "A Neural Network Based Approach for Testing Analog Circuits with Frequency Domain Classification and Time Domain Testing,'' Proc. IEEE System Test and Diagnosis Workshop, Sept. 1999.

    • S. Jandhyala, H. Balachandran, and A. Jayasumana, "Clustering Based Techniques for IDDQ Testing,'' Proc. International Test Conference, Sept. 1999.
    • S. Jandhyala, H. Balachandran, S. Menon, A. Jayasumana, "Clustering Based Identification of Faulty ICs Using IDDQ Tests, '' Proc. 1998 IEEE International Workshop on IDDQ Testing, Oct. 1998.
    • S. Wu, Y.K. Malaiya and A.P. Jayasumana, "Antirandom vs. Pseudorandom Testing,"  Proc. IEEE Int. Conf. on Computer Design, Oct. 1998, pp. 221-3.
    • S. Menon, A. P. Jayasumana and Y. K. Malaiya, ``BiCMOS Domino: A Novel High-Speed Dynamic BiCMOS Logic,'' International Journal of Electronics, Vol. 83, No. 2, pp 177-89, 1997.
    • S. Menon, A. P. Jayasumana and Y. K. Malaiya, "ECL Storage Elements: Modeling of Faulty Behavior,'' IEEE Transactions on Circuits Systems-II: Analog and Digital Signal Processing, Vol.44, No. 11, pp. 970-974, November 1997.

    • S. M. Menon, Y. K. Malaiya, A. P. Jayasumana and Q. Tong, ``Operational and Test Performance in the Presence of Built-in Current Sensors,'' Journal of VLSI Design, Vol. 5, No. 3, pp. 285-98, 1997.
    • W. K. Al-Assadi, A. P. Jayasumana and Y. K. Malaiya, ``IDDQ Testable Static RAM Design,'' Proceedings of the NASA Symposium on VLSI Design, March 1997.
    • S.M. Menon, Y.K. Malaiya and A.P. Jayasumana, ``Input Pattern Classification for Detection of Stuck-on and Bridging Faults Using IDDQ Testing in BiCMOS and CMOS Circuits,'' Proc. IEEE International Conference on VLSI Design, Jan. 1997. *
    • S. Menon, A. P. Jayasumana and Y. K. Malaiya, ``Input Pattern Classification for Transistor Level Testing of Bridging Faults in BiCMOS Circuits,'' Proc. Great Lakes Symposium on VLSI, March 1996.
    • W. A. Al-Assadi, A.P. Jayasumana, and Y.K. Malaiya, ``A Bipartite, Differential, IDDQ Testable Static RAM Design,'' Proc. IEEE International Workshop on IDDQ Testing (IDDQ'95), Oct. 1995, pp. 54-59.

    • W. A. Al-Assadi, A.P. Jayasumana, and Y.K. Malaiya, ``A Bipartite Differential IDDQ Testable Static RAM Design,'' Proc. IEEE International Workshop on Memory Technology, Design and Testing , Aug 1995, pp. 36-45.
    • S.M. Menon, A.P. Jayasumana, and Y.K. Malaiya, ``A Novel High-Speed BiCMOS Domino Logic Family,'' Proc. IEEE International Symposium on Circuits and Systems (ISCAS), April 1995, pp. 21-24.
    • S. M. Menon, Y. K. Malaiya, A. P. Jayasumana, and R. Rajsuman, ``Testable Design of BiCMOS Circuits for Stuck-Open Fault Detection using Single Patterns,'' IEEE Journal of Solid State Circuits, Vol. 30, No. 8, Aug. 1995, 855-63.
    • K. Mody and A. P. Jayasumana, ``An Efficient Multi-Layer Diagonal Router for Printed Circuit Boards,'' Computers and Electrical Engineering - An International Journal, Vol. 21, No. 3, May 1995, pp. 147-58. (Available from ScienceDirect)
    • S. M. Menon, A. P. Jayasumana and Y. K. Malaiya, ``Manifestation of Faults in Single- and Double-BJT BICMOS Logic Gates,'' Proceedings of IEE, Part E: Computers and Digital Techniques, Vol. 142, No. 2, March 1995, pp. 135-44.


    Papers on Eye Tracking and Gaze Tracking

    • N. M. Piratla and A.P. Jayasumana, ``A Neural-Network Based Gaze Tracker,'' Intelligent Engineering Systems Through Artificial Neural Networks, (Editors: Dagli, Buczak, Ghosh, Embrechts and Ersoy), Vol. 9 (Smart Engineering System Design), pp869-875, ASME Press, 1999. Also presented at ANNIE 99
    • N. M. Piratla and A. P. Jayasumana, ``A Neural Network Based Real-Time Gaze Tracker,''  Journal of Network and Computer Applications,  Vol. 25/3,  pp. 179-196, 2002   (pdf)

       



    PROCEEDINGS AND SPECIAL ISSUES

    • Y. K. Malaiya and A. P. Jayasumana (Editors), Digest of Papers - IEEE International Workshop on IDDQ Testing , Washington D.C., Oct. 1995.
    • C. Tong and A. P. Jayasumana (Editors), Digest of Papers - IEEE International Workshop on IDDQ Testing, Washington D.C., Published by IEEE-CS Press, ISBN 0-8186-7657-8, 115 pages, Oct. 1996.
    • A. P. Jayasumana and C. Tong (Editors), Digest of Papers - IEEE International Workshop on IDDQ Testing, Washington D.C., Published by IEEE-CS Press, ISBN 0-8186-8123-3, 120 pages, Oct. 1997.
    • A. P. Jayasumana and V. Chandrasekar (Editors), Technologies, Protocols, and Services for Next-Generation Internet, SPIE, Bellingham, Wash., USA : Aug. 2001, TK5105.55 .T43 2001.
    • M. Wahlisch, D. Turgut, T. Pfeifer, A. P. Jayasumana,  Current and future architectures, protocols, and services for the Internet of Things, Special Issue, Computer Communications, Volume 74, 2016,  ISSN 0140-3664, https://doi.org/10.1016/j.comcom.2016.01.003.

    • L. J. G. Villalba, J. Bi, A. P. Jayasumana and A. L. S. Orozoco, Advances on Software Defined Sensor, Mobile and Fixed Networks, International Journal of Distributed Sensor Networks, June 2016.





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