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IEEE 58th International
Midwest Symposium on Circuits and Systems

August 2-5, 2015, Fort Collins, Colorado Climbing to New Heights

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7 half-day tutorial sessions will be held on Sunday, August 2. Student registration for tutorials is $50/each and non-students registration is $75/each.
(click on the tutorial title to display the description)

Tutorial 1: The Journey to the FinFETs
Organizer/Presenter: Alvin Loke, Qualcomm Inc, USA

Description: Despite increasing economic and technical challenges to scale CMOS, we continue to witness unprecedented performance with second-generation fully-depleted tri-gate devices entering production at the 14nm node. This tutorial offers an intuitive summary of how CMOS device technology has progressed over the past two decades. We will review MOS device and short-channel fundamentals to motivate how device architectures in manufacturing have evolved to incorporate channel engineering, mechanical strain, high-K dielectric and metal gate, fully-depleted operation, and finally tri-gate finFETs

Tutorial 2: Design Methodology and Circuit Techniques for Any Load Stable LDO Regulators with Instant Load Control
Organizers/Presenters: Igor M. Filanovsky and Vadim Ivanov, University of Alberta, Canada and Texas Instruments, USA

Description: Application of the structural methodology to the LDO design creates a new class of circuits: any load stable, with instant transient response, large power supply rejection ratio and low noise. Presented are examples of the imbedded in SoC LDOs for the SRAM unit, (5 ns reaction time on the load steps), radio transmitter (shaping the required noise vs. frequency characteristic) and LDO for memory retention in the shutdown state (300 nA quiescent current). These LDOs can operate with or without off-chip load capacitors; they are robust to the process and temperature variations and portable to any CMOS process. The circuit techniques demonstrated during this course is proven in design of industrial circuits including LDO regulators.

The particular topics covered in this tutorial include:

  • Introductory. LDO regulators, their parameters in steady-state and dynamic operation. Line and load regulation. Load step response. Traditional topologies of LDO regulators, components of traditional regulators. The limitations of traditional one-loop regulators topologies.
  • General characteristics of the proposed approach: deep structural modifications. Using specialized two and multi-loop structures, error-dependent biasing and nonlinear amplifiers.
  • Traditional blocks for analog design. New blocks: current and transconductance amplifiers, their static and dynamic properties.
  • New nonlinear blocks: maximum and minimum selectors. Amplifiers with input impedance discriminating common-mode and differential mode signals.
  • Review of compensation techniques. First order frequency dependent transfer function. Examples of block realizations providing first order transfer functions. Step-transient response of the first order transfer functions. Second order frequency dependent transfer functions. Second order TF as a limit for loop gain frequency characteristic. Step transient response of second order transfer functions.
  • Nonlinear amplifiers. Examples.
  • Protection of power devices. Current and temperature limits. Load protection.
  • LDO design requirements.
  • Four LDO design examples: a) for fast load step response, b) for low noise, c) for high PSRR, d) for nano-power quiescent current.
  • Verification of design robustness.

Tutorial 3: Design by Mathematics: Full Software Radio Circuits and Systems in 28nm FDSOI Technology for 5G Standard and Beyond
Organizers/Presenters: Yann Deval, François Rivet, and Yoan Veyrac, Bordeaux Institute of Technology and University of Bordeaux, France

Description: The diversity of communication standards implies the use of multi-band and multi-mode radios. Recent years have seen a wide investigation on Software Defined Radio for Cognitive Radio application. But, this is always constrained to multi-standards prospectives while a complete agility of RF transceivers is required. That is why Full Software Radio proposes to challenge a new way of integrating RF circuits and systems by tackling the main issue: transceiving concurrently any RF signal within a very wide band of interest for telecommunication industry, from 0 to 5GHz for instance. It is clearly observed that disruptive solutions are required. The focus of this tutorial will be on the design by mathematics of such RF transceiver design, exploring novel approaches along with a thorough discussion of advanced techniques for these receivers and transmitters towards a revolution in RF integrated circuits and systems. 28nm FDSOI technology from STMicroelectronics will be detailed to demonstrate its strengths in RFIC design. First, a frequency system is presented using a Sampled Analog Signal Processor as a receiver and a Walsh frequency combiner for the transmitter. Then, a temporal system is presented using a wide-band delta analog to digital converter as a receiver and a RF arbitrary waveform generator, named Riemann Pump for the transmitter. The methodology of every approach will be detailed following the same flow: mathematics, trade-off with RF electronics integration in 28nm FDSOI, architecture proposal, high level simulation results, circuit design issues, measurement results. Finally, an application to 5G standard will be addressed by demonstrating the feasibility of such systems to carrier aggregation, wide-band capabilities, low power consumption and high order of modulation schemes.

Tutorial 4: Microprocessor Power Delivery Challenges in the Nano-Era
Organizer/Presenter: Mondira Pant, Intel Corp, USA

Description: A robust power grid is pivotal in meeting performance targets and guaranteeing reliable operation of high-performance microprocessors. Higher device densities and faster switching frequencies cause large switching currents through flow through the power and ground networks which degrade performance and reliability. Excessive resulting voltage drops in the power grid reduce switching speeds and decrease noise margins of the circuits and inject noise which may lead to functional failures. Further, high average current densities lead to undesirable wearing out of metal wires due to electro-migration. Achieving and maintaining excellent voltage regulation at the consumption points notwithstanding the wide fluctuations in the power demands across the chip is definitely the key to avoiding an unruly power grid. The tutorial plans to discuss not only the fundamentals of on-die power delivery but also the chief challenges involved in designing a robust and reliable power grid including verification against design targets using in-house/vendor tools in the nano-era.

Tutorial 5: Frequency Generation for the Internet of Things
Organizer/Presenter: Danielle Griffith, Texas Instruments, USA

Description: The emerging Internet of Things (IoT) market requires radios that operate with very low average power consumption to enable battery life measured in years, or even battery-free operation. This tutorial will introduce seven types oscillators used in these IoT radios, explaining how the low power requirements influence the oscillator architecture, design, and performance targets. The radio in an IoT wireless node is typically aggressively duty-cycled to reduce average power consumption. The wireless node spends the majority of time in sleep to conserve power, waking only occasionally to send or receive data packets. To synchronize these data packets among wireless nodes, a sleep timer is needed. The total system power is then limited by the sleep power and the sleep timer frequency stability. Four types of oscillators that can be used as a sleep timer will be described in detail: low frequency crystal oscillators, temperature compensated crystal oscillators, MEMS oscillators, and integrated oscillators, including design examples and power/accuracy tradeoffs. Standards used in IoT applications, such as Bluetooth Low Energy, also have reduced performance requirements allowing the radio to be optimized for low power operation. The radio PLL requires two oscillators: a high frequency voltage controlled oscillator, usually implemented as an LC oscillator, and a lower frequency reference oscillator, usually implemented as a crystal oscillator in the MHz range. Possible architectures, design examples, and tradeoffs will be described for each of these oscillators. Finally, IoT applications require a system clock for operating the microprocessor or peripherals when the radio is not enabled. This system clock can be implemented in various ways, such as a ring oscillator or current starved oscillator. Requirements and design considerations will be presented. At the end of the tutorial, attendees will have a solid overview of the many types of oscillators present in a typical IoT wireless node and understand design trade offs for each.

Tutorial 6: Calibration Techniques for Pipelined ADCs
Organizer/Presenter: Bibhudatta Sahoo, Amrita Vishwa Vidyapeetham University, India

Description: The alarming rate at which the transistor sizes have been shrinking in the past decade poses great challenges for analog and mixed-signal circuits that interface with real-world signals. However, this scaling trend has provided the IC industry with faster and cheaper transistors suitable for digital circuits. The analog-to-digital interface is the performance bottleneck in most mixed-signal or communication systems. We have reached an inflection point in the design of these interfaces: the “analog” designer must now know much more than analog design. The modern analog designer needs to capitalize on the immense DSP capabilities available in the current low voltage-nanometer-CMOS technologies. Time has therefore come to use thousands of “digital” transistors as a workhorse for a handful of analog transistors, thus unleashing a new era of digitally calibrated analog-to-digital converters (ADCs). This tutorial begins with an introduction to the scaling trend in transistors and power dissipation trends of data converters. Design challenges of pipelined ADC in nanometer CMOS will be discussed followed by a discussion on strategies/methodologies for designing high-resolution, low-power, and high-speed pipelined ADC. The tutorial will then comprehensively cover various analog and digital calibration techniques that have been developed over the last two-decades.
List of topics:
1. Scaling trend and its impact on analog design
2. Pipelined ADCs
3. Calibration techniques for pipelined ADCs

Tutorial 7: Design of Secure and Anti-Counterfeit Integrated Circuits
Organizer/Presenter: Shahab Ardalan, San Jose State University, USA

Description: In recent years, there has been a rapid innovation in the field of portable devices which has revolutionized the whole electronic market. The personalized gadgets such as smartphones are part of users’ life which contain sensitive data and private information. Privacy and protection of the data is a crucial task, consequently so many encryption techniques have been introduced to keep the data out of the hands of hackers. However, hackers employed new techniques that often proved the vulnerability of the crypto-processors. It is therefore imperative that system architects, circuit designers be aware of the security issue and be familiar with techniques to tackle such a rapidly growing threat. In light of the great importance to the new design dimension, security, this talk is proposed to provide an insight into and understanding of security challenges in design of digital circuits, identify the security requirements and present approaches leading to designing secure Cryptosystem-on-Chip (CoC).