Leon Chua, Univ. of California, Berkeley
Abstract: What is a memristor? Why is it called the 4th circuit element? Why did it take 37 years to make a memristor? Why did the HP memristor generate so much excitements? How does the memristor retain its memory even after the power is switched off? What is the difference between a non-volatile memristor and a locally-active memristor? How smart are memristors? This talk reminisces the conceptual genesis of the memristor in 1971 along with an in-depth circuit-theoretic characterization and generalizations. In particular, pinched hysteresis loops will be identified as the universal fingerprint of memristive systems, thereby unifying a broad class of non-volatile memories based on resistance switchings, such as RRAMs, MRAMs, phase-change memories, etc., published over the past two decades, as memristors. Future generalizations to memristor-based systems and ion channels will also be delineated and proposed as the right stuff for building low-power, laptop size and adaptive brain-like computers that could outperform existing supercomputers in many tasks, e.g. face recognition and dynamic associative memory.
Prof. Leon Chua received his MS and Ph.D. degrees from Massachusetts Institute of Technology and the University of Illinois at Urbana-Champaign. Since 1970, he has been with the University of California, Berkeley, where he is currently a Professor of Electrical Engineering and Computer Sciences.
He was the first recipient of the IEEE Gustav Robert Kirchhoff Award in 2005 and was awarded the IEEE Neural Networks Pioneer Award in 2000. Elected an IEEE Fellow in 1974, he has received many international prizes, including the IEEE Browder J. Thompson Memorial Prize, the IEEE W.R.G. Baker Prize, the Frederick Emmons Award, the M.E. van Valkenburg Award (twice), and the 2005 Francqui Award from Belgium.
He has been awarded seven USA patents and 15 Honorary doctorates from universities in Europe and Japan.
He was elected a foreign member of the European Academy of Sciences and the Hungarian Academy of Sciences. In 2010, he was awarded a John Guggenheim Fellow and the Leverhulme Trust Visiting Professorship. In 2011, he was conferred an Honorary Member of the Institute of Advanced Study at the Techniche Universitat Munchen, Germany, and also a Royal Academy of Engineering Distinguished Visiting Fellowship within Imperial College London. In 2013-2015 he was awarded the Marie Curie Fellowship by the European Commission.
Jae Cheol Son, Senior VP, Samsung
Abstract: Recent years, the advent of smart mobile devices enabled people living in an era of rapid technological changes, called the smart revolution. As new user interface and various mobile services have shown up continuously, mobile ecosystem and its devices keep evolving to meet various requirements from prosumers. Within the next few years, IoT based devices will lead the technological changes enabling the world truly connected and intelligent. The smart devices can be seen from small wearable devices to home appliances, autonomous vehicles, even infrastructure. The IoT device market will expand rapidly with people’s creative imagination. As the devices are getting smarter, SoC will keep playing the key role as it did for smart phones and tablet devices. Higher the performance and vivid user experience requires, performance and complexity of SoC is increased consistently. However, the competitive mobile SoC design comes from not only the performance of integrated IPs, but also other technologies such as power management, thermal control, and corresponding software solution. Having optimal silicon process technology is also important to meet the requirement in terms of performance, area and power consumption. This presentation will discuss the mobile SoC design trends from the time when smart revolution started and key upcoming technological challenges for mobile SoC.
Dr. Jae Cheol Son is currently a Senior Vice President at Processor Development Team of Samsung Electronics, where he leads the high-performance mobile CPU and GPU development. Prior to joining Samsung Electronics, he held various management and engineer positions at Sun Microsystems and Luminous Networks, where he focused on development of high-performance RISC microprocessors and advanced ASIC products. He received B.S. degree from Yonsei University, Seoul, Korea, and M.S. and Ph.D. degrees from KAIST, Daejeon, Korea, all in electrical engineering. His research interests include high-performance microprocessor design in deep submicron technology, multimedia processing, and statistical signal processing. He is a senior member of IEEE.
Sam Naffziger, Corporate Fellow, AMD
Abstract: Moore’s law has enabled not only higher levels of integration and performance, but has provided a well-documented improvement in energy efficiency gains for computation over the last decades. This rate of improvement in efficiency has seen a marked slowdown in recent years however as CMOS scaling has hit some fundamental limits to operating voltage and Vth reduction. Meanwhile the pressure on processor designers to reduce power and improve efficiency, both for mobile devices and for server computation, has never been greater. These conflicting factors have resulted in tremendous innovation around energy efficiency techniques based on circuit capabilities and advanced workload-adaptive power management algorithms which squeeze out far more computation per average Joule consumed than Moore’s Law enables. This talk will explore these trends, the efficiency technologies and the outlook for the future regarding further gains.
Sam Naffziger is a Corporate Fellow at AMD responsible for low power technology development, and has been the key innovator behind many of AMD’s low power features. He has been in the industry 27 years with a background in microprocessors and circuit design, starting at Hewlett Packard, moving to Intel and then at AMD since 2006. He received the BSEE from CalTech in 1988 and MSEE from Stanford in 1993 and holds 115 US patents in processor circuits, architecture and power management. He has authored dozens of publications and presentations in the field and is a Fellow of the IEEE.
Jim Warnock, IBM Distinguished Engineer
Abstract: Even for the largest servers, the era of continuing predictable frequency increases has ended, as is apparent when looking back at the history of the last several generations of server processors. However, this does not mean that digital circuit designers will be able to relax. High-end chip frequencies will likely need to stay roughly constant in the 4-5 GHz range as technology scaling continues, placing substantial stress on the design (and designers) as voltages are inevitably lowered in the face of power and reliability challenges from shrinking transistor dimensions. At the same time, the growth in the number of transistors per processor core, and the number of cores per chip will continue, as engineers try to squeeze out ongoing performance improvements in a world of constant core frequency. Digital circuit designers will need to be able to take on much larger chunks of the design, using ever more sophisticated EDA tools and synthesis engines in order to manage large-scale design planning activities, embedded IP blocks, and hierarchical optimization of interconnect wiring.
Jim Warnock, is a Distinguished Engineer in IBM’s Systems Unit. He received a B.Sc. degree from Ottawa University, Canada, and a PhD degree in physics from the Massachusetts Institute of Technology. Since then, he has been at IBM in Yorktown Heights, NY, working on high-speed microprocessors including POWER4, the Cell Broadband Engine, POWER7, and several z Systems designs. His interests include VLSI circuits, clocked storage elements, DFT, and design-technology interactions. He is a member of IBM’s Academy of Technology, and an IEEE Fellow.
Ken Stewart, Fellow, Intel
Abstract: LTE continues to make progress to define new features and functionality, ranging for advanced carrier aggregation modes to machine type communications (MTC). At the same time, new concepts for 5G systems are coming into focus. This presentation describes the latest advances in LTE air interface and device design, and then considers the emerging class of 5G air interface proposals in both the cm-wave and mm-wave bands, along with the changes to network and device architectures and technology required to support the 4G-5G transition by 2025.
Dr. Kenneth (Ken) Stewart is Chief Wireless Technologist, Intel Wireless Products R&D team, and Intel Fellow. In this role he contributes to innovation in wireless system-on-chip solutions, cellular and connectivity transceiver solutions, codecs, radio access offloading and routing, and location systems.
Most recently, Dr. Stewart was Chief Technology Officer for TE Connectivity’s Wireless business unit. He led the development, delivery and deployment of conventional and CPRI-based advanced multi-wavelength digital distributed antenna systems (DDAS), including low- and high-power multi-band multi-carrier remote radio heads (RRH) for LTE, WCDMA/HSPA, CDMA and 802.11. He drove the implementation of TE’s first Gbps optical switching fabric for the flexible delivery of capacity within the network, TE’s first hybridized small cell and DDAS RAN implementation, and the integration of TE’s advanced DDAS systems with its rapid fiber deployment technology.
Previously, Dr. Stewart was Vice President, Standards and Research at Motorola Mobile Devices, where he led the Standards and Research Lab which made contributions to the creation of 3GPP’s LTE specification, and previously the WCDMA HSDPA and HSUPA specifications. In this period he served as advisor to Motorola senior leadership on technical and strategic issues in radio access networks and multimedia. In his career at Motorola, Dr. Stewart designed and productized advanced wireless solutions for LTE, WCDMA and CDMA base stations and terminals, interference-suppressing MIMO receivers, WiFi offloading and traffic routing middleware and next-generation audio codecs.
Dr. Stewart has served as Motorola Dan Noble Fellow and Motorola Science Advisory Board member and holds more than 80 issued patents. He is a graduate of the University of Strathclyde, where he is also Visiting Professor.
Hossein Hashemi, Univ. of Southern California
Abstract: In 1965, Gordon Moore predicted that advancement in integrated circuit technology will enable monolithic microwave phased arrays that can revolutionize radar. Nearly four decades later, monolithic microwave silicon phased arrays were reported for the first time. Today, monolithic radio frequency, microwave, and millimeter wave phased arrays are turning mainstream in commercial products including automotive radars and high speed wireless transceivers. More recently, monolithic optical phased arrays have been reported promising applications such as projection, imaging, communications, and ranging. This talk will cover the basics, history, and applications of phased arrays followed by state-of-the-art realizations from radio frequencies up to optical.
Hossein Hashemi is a Professor of Electrical Engineering, Ming Hsieh Faculty Fellow, and the co-director of the Ming Hsieh Institute and the Ultimate Radio Laboratory (UltRa-Lab) at the University of Southern California. His research interests include analog, mixed-signal, and radio-frequency integrated circuits; electro-optical integrated systems; and implantable integrated solutions. He received the B.S. and M.S. degrees in Electronics Engineering from the Sharif University of Technology, Tehran, Iran, in 1997 and 1999, respectively, and the M.S. and Ph.D. degrees in Electrical Engineering from the California Institute of Technology, Pasadena, in 2001 and 2003, respectively. Dr. Hashemi currently serves on the Technical Program Committees of IEEE International Solid-State Circuits Conference (ISSCC), IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, and the IEEE Compound Semiconductor Integrated Circuits Symposium (CSICS). He is also an Associate Editor for the IEEE Journal of Solid state Circuits (2013 – present), and Guest Editor of the same journal for October 2013 and December 2013 issues. He was a Distinguished Lecturer for the IEEE Solid-State Circuits Society (2013 – 2014), an Associate Editor for the IEEE Transactions on Circuits and Systems—Part I: Regular Papers (2006–2007), and an Associate Editor for the IEEE Transactions on Circuits and Systems—Part II: Express Briefs (2004–2005). He was the recipient of the 2008 Defense Advanced Research Projects Agency (DARPA) Young Faculty Award and the National Science Foundation (NSF) CAREER Award. He received the USC Viterbi School of Engineering Junior Faculty Research Award in 2008, and was recognized as a Distinguished Scholar for the Outstanding Achievement in Advancement of Engineering by the Association of Professors and Scholars of Iranian Heritage in 2011. He was a co-recipient of the 2004 IEEE Journal of Solid-State Circuits Best Paper Award for “A Fully-Integrated 24 GHz 8-Element Phased-Array Receiver in Silicon” and the 2007 IEEE International Solid-State Circuits Conference (ISSCC) Lewis Winner Award for Outstanding Paper for “A Fully Integrated 24 GHz 4-Channel Phased-Array Transceiver in 0.13um CMOS based on a Variable Phase Ring Oscillator and PLL Architecture”. He is the co-editor of the book “Millimeter-Wave Silicon Technology: 60 GHz and Beyond” published by Springer in 2008.