Best Paper Award Nominees
The following three papers were selected as candidates for the Best Paper Award.
- NoC-enabled Software/Hardware Co-Design Framework for Accelerating k-mer Counting
Biresh Kumar Joardar (Washington State University), Priyanka Ghosh (Washington State University), Partha Pratim Pande (Washington State University), Ananth Kalyanaraman (Washington State University), and Sriram Krishnamoorthy (Pacific Northwest National Laboratory) - SMART++: Reducing cost and improving efficiency of multi-hop bypass in NoC routers
Iván Pérez, Enrique Vallejo and Ramón Beivide (University of Cantabria, Santander) - APEC: Improved Acknowledgement Prioritization through Erasure Coding in Bufferless NoCs
Michael Vonbun, Adrian Schiechel, Nguyen Anh Vu Doan, Thomas Wild and Andreas Herkersdorf (Technical
University of Munich)
Presentation Guidelines
- Each accepted regular paper/special session paper/tutorial shall prepare an oral presentation in 25 minutes: 20 minutes for the talk and 5 minutes for Q&A.
- There is no template for oral presentations and authors are free to choose a proper template by themselves.
- In the break before the start of their session, the presenters of papers shall give his or her short bio to the session chair for timely introduction.
- Lightning talk for a work-in-progress (WIP) poster is 2 minutes with no time for Q&A. Participants may discuss their work with other attendees in front of their posters during the coffee break.
Final Program
NOCS 2019 will be held at the NYU Abu Dhabi HQ Building (19 Washington Square North, New York, NY).
| Thursday October 17, 2019 | |
| Time | Activity |
| 8:00-9:00 | Breakfast |
| 9:00-9:15 | Opening Remarks |
| 9:15-10:15 | Keynote I Session chair: Sudeep Pasricha (Colorado State University) "Interconnect Meets Architecture: On-Chip Communication in the Age of Heterogeneity" |
| 10:15-10:45 | Coffee Break |
| 10:45-12:00 | Regular Paper Session I: NoC and Router Design Session chair: Andreas Herkersdorf (Technical University of Munich) "UBERNoC: Unified Buffer Energy-Efficient Router for Network-on-Chip" "Ghost Routers: Energy-Efficient Asymmetric Multicore Processors with Symmetric NoCs" "BINDU: Deadlock-Freedom with One Bubble in the Network" |
| 12:00-12:30 | Invited Talk Session chair: Ajay Joshi (Boston University) "Accelerator Fabric in Facebook Zion Training System" |
| 12:30-14:00 | Lunch |
| 14:00-15:15 | Special Session 1: Interconnection Networks for Deep Neural Networks Session chair: Tushar Krishna (Georgia Institute of Technology) Session organizers: Kun-Chih (Jimmy) Chen (National Sun Yat-sen University), Masoumeh (Azin) Ebrahimi (KTH Royal Institute of Technology) "NoC-based DNN Accelerator: A Future Design Paradigm" "Energy-Efficient and High-Performance NoC Architecture and Mapping Solution for Deep Neural Networks" "Flow mapping and data distributing on mesh-based deep learning accelerator" |
| 15:15-15:30 | Lightning Talks for Work in Progress (WIP) Posters Session chair: Sudeep Pasricha (Colorado State University) "Reinforcement Learning based Interconnection Routing and Adaptive Traffic Optimization" "Power efficient Photonic Network-on-Chip for a Scalable GPU" "CDMA-based Multiple Multicast Communications on WiNOC for efficient parallel computing" "Channel Mapping Strategies for Effective Protection Switching in Fail-Operational Hard Real-Time NoCs" "Multi-Carrier Direct Sequence Spread Spectrum Transceiver for WiNoC" "Detection and Prevention Protocol for Black Hole Attack in Network-on-Chip" "Analyzing Networks-on-Chip based Deep Neural Networks" |
| 15:30-16:15 | WIP Posters and Coffee Break |
| 16:15-17:30 | Regular Paper Session 2: Best Paper Nominees Session chair: Paul Ampadu (Virginia Polytechnic Institute and State University) "NoC-enabled Software/Hardware Co-Design Framework for Accelerating k-mer Counting" "SMART++: Reducing cost and improving efficiency of multi-hop bypass in NoC routers" "APEC: Improved Acknowledgement Prioritization through Erasure Coding in Bufferless NoCs" |
| 19:00-21:00 | Banquet Location: |
| Friday October 18, 2019 | |
| Time | Activity |
| 8:00-9:00 | Breakfast |
| 9:00-10:00 | Keynote II Session chair: Ajay Joshi (Boston University) "Toward Fast Analysis and Exploration of Communication Fabrics" |
| 10:00-10:15 | Coffee Break |
| 10:15-11:30 | Tutorial 1: System on Package (SoP): A Holistic Approach for System Integration Session chair: Tushar Krishna (Georgia Institute of Technology) Speakers: Madhavan Swaminathan, Mohan Kathaperumal (Georgia Institute of Technology) |
| 11:30-12:30 | Tutorial 2: Engineering a specialized, high-performance network Session chair: Ishan Thakkar (University of Kentucky) Speakers: Brian Greskamp, Keun Sup Shim (D.E. Shaw Research) |
| 12:30-14:00 | Lunch |
| 14:00~15:40 | Regular Paper Session 3: NoC Potpourri Session chair: Maurizio Palesi (University of Catania) "ClusCross: A New Topology for Silicon Interposer-Based Network-on-Chip" "Distributed SDN Architecture for NoC-based Many-core SoCs" "Approximate Nanophotonic Interconnects" "Direct-Modulated Optical Networks for Interposer Systems" |
| 15:40-16:00 | Coffee Break |
| 16:00-17:15 | Special Session 2: Heterogeneous Integration and Interconnect Fabrics Session chair: Ishan Thakkar (University of Kentucky) "3D NoCs with Active Interposer for Multi-Chip Module" "Global and Semi-Global Communication on Silicon Interconnect Fabric" "A 7.5-mW 10-Gb/s 16-QAM Wireline Transceiver with Carrier Synchronization and Threshold Calibration for Mobile Inter-chip Communications in 16-nm FinFET" |
| 17:15-17:30 | Closing Remark with Best Paper Announcement |
Keynote Talks
Keynote I
Date: Thursday October 17, 2019
Time: 09:15-10:15
Speaker: Partha Pratim Pande (Washington State University)
Title: Interconnect Meets Architecture: On-Chip Communication in the Age of Heterogeneity
Abstract:
The design of data centers is dominated by power, thermal, and physical constraints. On the contrary, emerging heterogeneous manycore processing platforms that consist of CPU and GPU cores along with memory controllers (MCs) and accelerators have small footprints. Moreover, they offer power and area-efficient tradeoffs for running big data applications. Consequently, heterogeneous manycore computing platforms represent a powerful alternative to the data center-oriented type of computing. However, typical Network-On-Chip (NoC) infrastructures employed on conventional manycore platforms are highly sub-optimal to handle specific needs CPUs, GPUs and accelerators. To address this challenge, we propose a holistic approach to design an optimal network-on-chip (NoC) as the interconnection backbone for the heterogeneous manycore chip that can handle CPU, GPU and application-specific accelerator communication requirements efficiently. We will discuss design of a hybrid NoC architecture suitable for heterogeneous manycore platforms. We will also highlight efficacy of machine learning-inspired multi-objective optimization algorithms to quickly find a NoC that satisfies both CPU and GPU communication requirements.
Partha Pratim Pande is a Professor and holder of the Boeing Centennial Chair in computer engineering at the school of Electrical Engineering and Computer Science, Washington State University, Pullman, USA. He is currently the director of the school. His current research interests are novel interconnect architectures for manycore chips, on-chip wireless communication networks, and heterogeneous architectures. Dr. Pande currently serves as the Associate Editor-in-Chief (A-EIC) of IEEE Design and Test (D&T). He is on the editorial boards of IEEE Transactions on VLSI (TVLSI) and ACM Journal of Emerging Technologies in Computing Systems (JETC). He was/is the technical program committee chair of IEEE/ACM Network-on-Chip Symposium 2015 and CASES (2019-2020). He also serves on the program committees of many reputed international conferences. He has won the NSF CAREER award in 2009. He is the winner of the Anjan Bose outstanding researcher award from the college of engineering, Washington State University in 2013.
Keynote II
Date: Friday October 18, 2019
Time: 09:00-10:00
Speaker: Raid Ayoub (Intel Labs)
Title: Toward Fast Analysis and Exploration of Communication Fabrics
Abstract:
Communication fabrics have become an integral part of modern computing systems, ranging from Systems-on-Chips to data centers and beyond. They are critical to system’s performance as well as power since they are major shared resources in the systems. Modern system level evaluation and exploration simulation tools include the communication fabric as an essential component. However, existing accurate simulation tools for the communication fabrics are notoriously slow. Moreover, emerging applications require longer simulations that become prohibitively expensive. There is a growing need for scalable, fast, and accurate simulation frameworks for the communication fabrics. In this talk, I will discuss these challenges and cover some recent advancements in this domain. For example, I will discuss techniques related to systematic generation of accurate and fast high-level models of the Network-on-Chips with priority classes using queuing theory combined with machine learning. Then I will conclude with possible research directions in this domain.
Raid Ayoub received his Ph.D. degree in computer engineering from the department of computer science and engineering, University of California at San Diego in 2011. Currently he is a research scientist at Intel Labs of Intel Corporation. He has published over 30 journal and conference papers. His research interests include high-level system modeling of emerging applications with a particular interest in communication networks, runtime optimizations and dynamic control, machine learning, design automation, IoT systems, queuing theory, and system energy efficiency.
Special Sessions
Special Session 1: Interconnection Networks for Deep Neural Networks
Date: Thursday October 17, 2019
Time: 14:00-15:15
Organizers: Kun-Chih (Jimmy) Chen (National Sun Yat-sen University), Masoumeh (Azin) Ebrahimi (KTH Royal Institute of Technology)
Abstract:
Deep Neural Networks (DNN) have shown significant advantages in many domains such as image processing, speech recognition, and machine translation. The contemporary DNN comprises of tens to thousands of layers, which are largely computation and communication intensive. General-purpose processors are not capable of efficiently handling this huge amount of data in an acceptable time. To tackle this issue, the design of DNN accelerators has received much attention from both academia and industry in recent years. The focus of these architectures is mainly on efficient computations with little attention on proper communication. The intensive communication among neurons in different layers leads to complicated interconnection patterns that lack flexibility and scalability while suffering from extensive memory accesses.
To reduce the gap between the efficiency of DNN computation and communication and to reduce the complexity of interconnections, there is a need to design and develop proper high-performance and flexible interconnection networks. Among the possible approaches, Network on Chip (NoC) is one of the viable solutions to meet the performance and design productivity requirements of the complex on-chip communication. The NoC- based DNN design paradigm, offering a regular and flexible structure, can become a potential and efficient way to construct a large-scale DNN accelerator in future. The special session is motivated by these reasons and aims at rising the contributions on efficient interconnect solutions for deep neural networks. The topics of interest include, but not limited to:
- Interconnection networks for DNNs (ANN, RNN, CNN etc.)
- Interconnection networks for the memory challenge in deep learning
- Interconnection networks for better power/latency efficiency in deep learning
- Interconnect-based neural network architecture design
- Automated design tools for the DNN interconnect design
- Interconnect-based neural network algorithm design
Special Session 2: Heterogeneous Integration and Interconnect Fabrics
Date: Friday October 18, 2019
Time: 16:00-17:15
Organizers: Baris Taskin (Drexel University), Boris Vaisband (McGill University)
Abstract:
With the evident slow-down in scaling of on-chip features, the focus of the integrated circuits community is shifting towards other, less explored scaling opportunities. One such opportunity is scaling features at the system level, for example, interposer, package, wafer-scale integration, and printed circuit board (PCB) technologies. In fact, on-chip features have scaled approximately 1,000x in last fifty years, whereas packaging features have only scaled approximately 4x within the same period of time. This notion provides an opportunity for scaling features at a higher hierarchical level, addressing important I/O bottlenecks (especially in von-Neumann architectures), and thus significantly increasing system performance.
Some of the integration technologies are relatively mature (i.e., interposers), whereas others, are quite outdated and require novel approaches to decrease feature dimensions (i.e., package and PCB). Additional, novel integration approaches such as the silicon interconnect fabric (Si-IF) [1], provide an opportunity for heterogeneous integration at the wafer scale with performance characteristics of a system-on-chip. Communication methodologies at all of these hierarchical integration levels must be developed to support higher bandwidth and lower energy of the integrated systems. In addition to higher performance, the system level integration platforms support integration of heterogeneous systems (e.g., processor-memory pairs, MEMS, RF circuitry, etc.) fabricated using dedicated (optimal) processes.
The special session will provide an opportunity for the networks-on-chip (NoCs) community to be exposed to novel research related to communication methodologies on various integration platforms and interconnect fabrics. The unique challenges of communication on such platforms will be presented, stimulating discussion and further research to tackle these issues and enable high performance heterogeneous integration. The special session aims to facilitate multidisciplinary research at various levels, including, circuits, algorithms, methodologies, and architectures, all of which are required to support high performance heterogeneous integration. This special session is unique since it aims to present research related to NoCs at novel integration platforms that are not addressed by the existing sessions in NoCs, such as interposers and the Si-IF.
[1] Subramanian S. Iyer, “Heterogeneous Integration for Performance and Scaling,” IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 6, No.7, pp. 973 – 982, July 2016.
Tutorials
Tutorial 1: System on Package (SoP): A Holistic Approach for System Integration
Date: Friday October 18, 2019
Time: 10:15-11:30
Speakers: Madhavan Swaminathan, Mohan Kathaperumal (Georgia Institute of Technology)
Abstract:
A combination of “Moore” (IC) and “More than Moore” (package) scaling has led to the shrinking of electronic systems over the last several decades. As scaling continues beyond CMOS to include advanced devices, scaling of the package needs to keep pace as well to enable further miniaturization. This requires new technologies for integration which when connected to SoC can lead to miniaturized solutions that have superior performance. Such a pseudo-lithic integration approach (as opposed to monolithic integration) can provide significant advantages in terms of enabling new system architectures, IP reuse, improved reliability, thermal management, robust power delivery, faster data rate and reduced system cost.
In this tutorial we cover the fundamentals of SoP technologies in the context of High Performance Computing (HPC) applications. This 1.5 hour tutorial will consist of three parts namely, i) Pseudo-lithic integration based architectures and their advantages in the context of signaling and power delivery. Here we will focus on integrated voltage regulators (IVR) for power delivery and the opportunities posed by advanced packaging technologies for high-speed signaling. We will compare these solutions to silicon interposer based solutions pursued by industry today through metrics such as data rate and eye opening. ii) Glass Panel Embedded (GPE) packaging for chip-to-chip communication which provide superior bandwidth and power efficiency as compared to other pseudo-lithic architectures. Using advanced process technologies, the tutorial will discuss embedded packages capable of supporting Si-like redistribution layers (RDL) along with superior electrical performance and reliability of glass. The tutorial will cover topics including various types of 2.5D and 3D GPE packages. The advanced processing technologies available to achieve this will be discussed while covering the fabrication of various types of cavities for die placement, multi-die embedding, RDL build up-layers with advanced low-k polymers, through glass vias (TGV), via filling and plating technologies. The advantages of using glass as a substrate and a carrier for die (multi-dies) embedding over other technologies will also be presented. iii) The assembled dies need to have the appropriate interconnection pitch to provide connectivity to the RDL layers in the package along with appropriate thermal management solutions to handle high heat fluxes and hot spots. Advanced assembly technologies including copper-to-copper bonding at fine pitch, thermal interface materials, vapor chambers and microfluidic cooling methods for heat removal will be discussed.
The tutorial will provide a holistic approach to system integration using SoP based technologies by covering design, materials, fabrication, assembly and thermal management related issues but at a level that can be understood by a system or chip designer. Hence, the goal of the tutorial is to capture the essence of SoP integration by providing details on the advances made in this area over a two decade period (rather than provide intricate details) and propose it as an alternative to monolithic SoC integration.
Tutorial 2: Engineering a Specialized, High-Performance Network
Date: Friday October 18, 2019
Time: 11:30-12:30
Speakers: Brian Greskamp, Keun Sup Shim (D.E. Shaw Research)
Abstract:
We will present our design experiences with the Anton 2 on- and off-chip network implementation. Emphasis will be placed on various network specializations for molecular dynamics and details of our engineering process. We will also talk about trends in technology and how they may influence directions in future interconnection network architectures.
Invited Talk
Title: Accelerator Fabric in Facebook Zion Training System
Date: Thursday October 17, 2019
Time: 12:00-12:30
Speaker: John Kim (KAIST/Facebook)
Abstract:
Zion is Facebook’s next generation machine learning training platform that consists of 8-node accelerators to provide the high compute capability in addition to 8 processors. The accelerator architecture adopts vendor-agnostic OCP accelerator module (OAM) and requires a unified platform for the different accelerator solutions. In this talk, we will present the accelerator fabric for the Zion system and in particular, the interconnect topology. We will also discuss the communication challenges with the deep learning recommendation models and how Zion can efficiently support the communication requirements.