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Now you've created a schematic in design architecture, with vhdl code, equ, pla or kiss.
You've carefully tested the functionality of your design in Quicksim II or QuickVHDL and you've
added the pads and buffers for the Xilinx board. Now you're ready to create a file of your design
to download.
- If you're not already in it, start design manager by typing pld_dmgr.
- In the right window, find the icon of the schematic for your design.
Select that icon with the right mouse button go to Open and 6 pld_men2xnf8.
- In the PLD XNF Translation window that opens set:
Part Type: 4008epc84
Run Memgen Only?: No
Verbose Output?: No
Help?: No
Then click on OK.
- A terminal window will open. If the XNF file is created successfully, you'll see a message
'Men2xnf8 ended with return code 0 Done', otherwise you'll get an error message. If you get an error
check the .out file fix the error and repeat this.
- If there were no errors in the previous step, find there should now be an icon in Design
Manager with Xilinx above it and xnf in the box and the design name underneath it.
Highlight this icon and with the right mouse go to Open and pld_xmake.
The Xilinx XMAKE Tool window that opens should have the following settings:
Override Part Type: No
Verbose Output?: No
Rerun All Steps?: No
Use Guide File?: No
Perform X-BLOX Optimization?: No
Generate MAK File Only?: No
Output to Screen?: No
Mapping Strategy?: None
Target?: Make Bitstream
Then click on OK.
- Another terminal window will open. If there are errors check the .out or .prp
files. If pld_xmake is successful, you'll see a message that the .bit file has been
created. If your going to download the file from another location, use ftp to send the .bit
file to that account.
- Make sure the power to the board is on, hit the reset switch on the board and from
the command line type xchecker design_name.bit and this file will download.
Next: Connecting the Xilinx Board
Up: Xilinx
Previous: Logic Synthesis From KISS
Geun Rae Cho
Tue Aug 24 19:15:12 MDT 1999