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Refer to the diagram Figure 1-3 FPGA Demonstration Board Component Layout on page 1-6 of
the Xilinx Development System for this section.
- Connect +5V to pin 1 of connector J9 and common to pin 2 of the same. Check the levels
of the power supply before you connect to the Xilinx board.
- The XChecker/Download Cable connects to J2 on the board. The pins are labeled 1-18 from
left to right and top to bottom and the cable connects as follows:
Pin 1: VCC
Pin 2: RT
Pin 3: GND
Pin 4: RD
Pin 6: TRIG
Pin 7: CCLK
Pin 9: D/P
Pin 11: DIN
Pin 13: PROG
Pin 15: INIT
Pin 16: CCKI
Pin 17: RST
Pin 18: CLKO
- The switches SW2 need to be up down down up up up up down, where up means
pushed in at the top.
- The switches at connector SW3 can be used as 8 inputs to the chip that you
can control by mapping your design to these corresponding ports.
See Table 1-2 FPGA Pin Connections.
- When you turn on power if everything is correct, the decimal points in the 7-segment LED's
at U6 and U7 will be lit.
Figure 7: Design Flow
Geun Rae Cho
Tue Aug 24 19:15:12 MDT 1999