Logic Synthesis From EQU Descriptions Using AutoLogicII

Equ Descriptions are ASCII files of Boolean equations you write with a text editor. The following is an example for a four bit adder.

1. Write a file with a .equ extension like the one that follows:

   net c1 c2 c3;
   s0 = a0 ^ b0 ^ cin;
   c1 = a0 & b0 | a0 & cin | b0 & cin;
   s1 = a1 ^ b1 ^ c1;
   c2 = a1 & b1 | a1 & c1 | b1 & c1;
   s2 = a2 ^ b2 ^ c2;
   c3 = a2 & b2 | a2 & c2 | b2 & c2;
   s3 = a3 ^ b3 ^ c3;
   cout = a3 & b3 | a3 & c3 | b3 & c3;

   The line net c1 c2 c3 means that c1, c2 and c3 are internal nets. Everything else are then inputs and outputs. Signal names must start with a numeric character. Logical operators must have a space before and after them. The Boolean operators are: - for NOT, & for AND, for XOR and | for OR.

2. Make a directory eddm.
3. Start AutoLogic by typing alui.
4. After the AutoLogic II window opens, go to Setup in the pull down menu then Destination Technology and then xc4ke/default and OK.
5. In the pull down menu go to File, Open and Design.... The settings are:

   File Format: EQU
   Options:
   Library:work
   Cell:design_name
   View:equ
   Files:design_name.equ
   

   Where design_name is the name of your .equ file.

6. In the pull down menu, go to Optimize then Optimize.... Make the settings:

   Optimization Type: Area
   Area Optimization Options: Medium
   Factor
   

7. Lastly, go to File in the pull down menu then Save and EDDM.

   Model Name: (leave blank)
   GN Library Mapping: work eddm
   select Generate Schematic
   

EQU synthesis creates a symbol but the pins are not sorted. Go to the section on Schematic Capture to see how to create a symbol to overwrite this one and add the ports and buffers to your design so that it can be downloaded to the Xilinx board. You will find the schematic sheet in the eddm directory.