next up previous
Next: Logic Synthesis From EQU Up: Xilinx Previous: Logic Synthesis From VHDL

Logic Synthesis From PLA Descriptions Using AutoLogicII

This section describes how you can use truth tables represented as a Programmable Logic Array files as inputs to AutoLogic II to produce simple combinational circuits.

  1. Write a text file like the one for a full adder that follows.

    .i 3
    .o 2
    .ilb a b cin
    .ob cout s    #This is a comment
    .type f
    .phase 111
    000 00
    001 01
    010 01
    011 10
    100 01
    101 10
    110 10
    111 11
    .e

    In this file, .i 3 means there are three inputs, .o 2 means there are two outputs. The line .ilb a b cin names the inputs and ob cout s names the outputs. The line .type f is a default setting which makes any combination of inputs not listed in the offset (they're '0'). The .phase 111 makes the outputs all active high. The next eight lines are the inputs and outputs as listed in the .ilb and .ob lines. Don't cares are denoted with a - and the file ends with .e. Each line must have a carriage return at the end.

  2. Make a directory eddm.
  3. Start AutoLogic by typing alui.
  4. After the AutoLogic II window opens, go to Setup in the pull down menu then Destination Technology and then xc4ke/default and OK.
  5. In the pull down menu go to File, Open and Design.... The settings are:

    File Format: PLA
    Options:
    Library:work
    Cell:design_name
    View:pla
    Files:design_name.pla

    Where design_name is the name of your .pla file.

  6. In the pull down menu, go to Optimize then Optimize.... Make the settings:

    Optimization Type: Area
    Area Optimization Options: Medium
    Factor

  7. Lastly, go to File in the pull down menu then Save and EDDM.

    Model Name: (leave blank)
    GN Library Mapping: work eddm
    select Generate Schematic

PLA synthesis creates a symbol but the pins aren't sorted. Go to the section on Schematic Capture to see how to create a symbol to overwrite this one and add the ports and buffers to your design so that it can be downloaded to the Xilinx board. You will find the schematic sheet in the eddm directory.


next up previous
Next: Logic Synthesis From EQU Up: Xilinx Previous: Logic Synthesis From VHDL

Geun Rae Cho
Tue Aug 24 19:15:12 MDT 1999