This section describes how you can use truth tables represented as a Programmable Logic Array files as inputs to AutoLogic II to produce simple combinational circuits.
.i 3
.o 2
.ilb a b cin
.ob cout s #This is a comment
.type f
.phase 111
000 00
001 01
010 01
011 10
100 01
101 10
110 10
111 11
.e
In this file, .i 3 means there are three inputs, .o 2 means there are two outputs. The line .ilb a b cin names the inputs and ob cout s names the outputs. The line .type f is a default setting which makes any combination of inputs not listed in the offset (they're '0'). The .phase 111 makes the outputs all active high. The next eight lines are the inputs and outputs as listed in the .ilb and .ob lines. Don't cares are denoted with a - and the file ends with .e. Each line must have a carriage return at the end.
File Format: PLA
Options:
Library:work
Cell:design_name
View:pla
Files:design_name.pla
Where design_name is the name of your .pla file.
Optimization Type: Area
Area Optimization Options: Medium
Factor
Model Name: (leave blank)
GN Library Mapping: work eddm
select Generate Schematic