Logic Synthesis From VHDL Using AutoLogicII

1. Start Autologic II by typing alui.
2. After the AutoLogic II window opens, go to Setup in the pull down menu then Destination Technology and then xc4ke/default and OK.
3. In the pull down menu go to File, Open and VHDL Library.... In the Open VHDL Library window select work.
4. When the VHDL Library Browser window opens, click on the + sign in front of your design. Click on the blue dot next to behavior, it should turn green.
5. In the pull down menu go to Setup and Technology Environment. Set the parameters as follows:

   Device Type: 4008epc84
   Speed Grade: -6
   Package Type: PLCC
   Number of Pins: 84
   Temperature Range: Commercial
   Enhanced Clock-Enable: No
   Macro Mapping Objective: Area
   Schematic configuration file: PADs on all levels
   

6. In the pull down menu go to Synthesize and Synthesize VHDL Design. The Synthesize VHDL Design window should have the following settings:

   Library: work
   Entity: design_name
   Architecture: behavior
   

   Where 'design_name' is the entity name in your VHDL file. When the synthesis is finished the Design Browser window should open.

7. If you have a clock in your design, click on the + sign next to the design name in the Design Browser window under the Netlist column. Click on the + that appears next to Nets. Click on the clock dot to select it and turn it green. Then from the pull down menu , go to Constraints then Add Constraints then Clock. Enter your clock period in the text box and click on OK.
8. Repeat Step 5.
9. In the pull down menu , go to Optimize then Optimize.... Make the settings:

   Optimization Type: Area
   Area Optimization Options: Medium
   Factor
   

10. Repeat Step 5.
11. Again go to Optimize then Optimize.... But this time use the settings:

    Optimization Type: Add/Remove IO cells
    All ports: yes
    Switch: add
    

12. Repeat Step 5.
13. Lastly, go to File in the pull down menu then Save and EDDM.

    Model Name: (leave blank)
    GN Library Mapping: work eddm
    select Generate Schematic
    

This process has created a symbol for your design. Now go to the section on Schematic Capture to see how to add the ports and buffers to your design so that it can be downloaded to the Xilinx board. You will find the schematic sheet in the eddm directory.