Anura Jayasumana

  » Publications

  »  Professional Activities
  » Patents

  » Teaching

  » Graduates

  » Research Projects

  » Dept Homepage



  • Patent No. US6028995: Method of determining delay in logic cell models, Mark Jetton and Anura P. Jayasumana, Issued Feb. 22, 2000 (Assignee - LSI Logic Inc.).

  • Patent No. US5757816: IDDQ Testing of Integrated Circuits, Waleed K. Al-Assadi, Anura P. Jayasumana and Yashwant K. Malaiya, Issued May. 26, 1998, (Assignee - Advanced Micro Devices (AMD), Austin, TX).