Lab Assignments
Lab sections meet in Room
C207 Engineering.
Labs start on Monday August 28th, 2017.
Policies:
Assignments & Instructions:
| Week |
Project Description |
| Aug 21 - 25 |
Create an Engineering
Network Account |
| Aug 28 - Sept 1 | Lab 1: Introduction to DE2 and Quartus II (Lab0.zip ) |
| Sept 5 - Sept 11 |
Lab 2: Schematic Entry,
Timing Diagrams and Functional Simulation using
Quartus II |
| Sept 12 - Sept 18 | Lab
3: Design,
Simulation and Verification of Combinational Circuits |
| Sept
19 - Sept 25 |
Lab
4: Two's Complement
Adder Subtractor Design |
| Sept
26 - Oct 2 |
Lab
5: The Array
Multiplier |
| Oct
3 - Oct 9 |
Lab
6: The Seven
Segment Display |
| Oct
10 - Oct 16 |
Lab
7: The Binary to
Seven-Segment Decoder |
| Oct
17 - Oct 23 |
Lab
8: An
Accumulator-based Tally Unit |
| Oct
24 - Oct 27 |
This
is a make-up week. Any late labs have to be completed and reports must be submitted during this week. There will not be another opportunity to complete labs 1-7 after this. TAs will not accept any demos or reports for Labs 1-7 after this week. Any incomplete lab will automatically result in an "F" for the course as stated in the outline. Lab 9 will be conducted from Monday, Oct 30. |
| Oct 30 - Nov 3 |
Lab 9: Shift Register and
Register Bank |
| Nov 6 - Nov 10 |
Lab 10: Design of Counters |
| Nov 13 - Nov 17 |
Lab 11: An Encryption Unit for
Serial Communication |
| Nov 27 - Dec 1 |
Lab 12: Nanoprocessor |
Downloads: