Compilation and Simulation

VHDL programs have to be compiled before they can be simulated. You need to QuickHDL tools to compile and simulate the VHDL models.

1. create a work directory by typing qhlib work_dir_name in the directory where the VHDL model is.
2. compile the VHDL source code by typing qvhcom vhdl_file_name -work work_dir_name in the directory where the VHDL model is.
3. simulate the VHDL model by typing qhsim design_name. The design_name is the entity name given in the model. Once inside the qhsim, execute a stimulus file to run the simulation. The format of a stimulus file is shown below. You can verify the results in the waveform window.

   wave -hex fun_sel a_in b_in alu_out
   force fun_sel 00 0
   force a_in  000 0
   force b_in  001 0
   run 10
   force a_in  011 10
   force b_in  011 10
   force a_in  010 20
   force b_in  101 20
   force a_in  101 30
   force b_in  011 30
   run 280