Program Entry

To enter a VHDL program for the Mentor Graphics software, you can either use your favorite text editor or the design architect VHDL subsystem. This document will focus on using a text editor to enter the source code, users wishing to use the design architect VHDL subsystem are referred to the online documentation. When using a text editor to enter VHDL source code it is best to give the file name an extension of .hdl. A VHDL source file has three sections.

1. the library statements. These statements are used to include precompiled code into your VHDL program. The most common library to be included into a VHDL program on the Mentor Graphics system is the mgc_portable library. This library contains data types and functions for interfacing to the Mentor Graphics simulation environment. To use the mgc_portable library include the following two lines at the top of your source code.

   LIBRARY mgc_portable;
   USE mgc_portable.qsim_logic.ALL;

2. the entity section. This part of a VHDL source file gives the input/output interface for a VHDL model. The various statements in the entity section give the name, type, and direction of all input/output signals for the model. An entity statement for a two input one output gate in the Mentor Graphics simulation environment would look like:

   ENTITY gate IS
     PORT (a, b : IN  qsim_state;
           y    : OUT qsim_state
     );
   END gate;

3. the architecture section. This section of a VHDL source file is the actual implementation of the desired function. VHDL has two types of executable statements:
   1. sequential
   2. concurrent
   Concurrent statements are scheduled for execution by the simulator at the same time. The actual execution order of the concurrent statements is not fixed and therefore cannot be relied upon to provide a desired result. The most common concurrent statement you will use is the PROCESS statement. This statement is used to schedule the execution of a series of sequential statements based upon activity in the model. The sequential statements in VHDL are similar to PASCAL or C in syntax and are well covered in the online documentation as are the concurrent statements. The architecture of our two input gate for a simple logic function would look like:

   ARCHITECTURE behave OF gate IS
   BEGIN
   bb: PROCESS (a,b)
   BEGIN
     y <= a OR b;
   END PROCESS bb;
   END behav;