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Debugging a VHDL program is similar to debugging any other program. The same two methods of attack,
diagnostic printouts and interactive debugging, are used. Diagnostic printouts are performed using the
ASSERT statement. This statement provides several classes of output:
- NOTE: This class of assertions can be used for general debugging output such as entry and exit of
processes and the value of internal variables. These assertions will not terminate execution of the
program.
- WARNING: This class of assertions is used for possible undesirable conditions such as an unknown
state in a finite state machine. Program execution is not terminated but the results may be wrong.
- ERROR: This class of assertions should be used for tasks that compete but give a wrong or
undesirable result. An example of a time to use the ERROR class would be for a divide by zero. Program
execution terminates.
- FAILURE: This class of assertions should be used for errors that would cause a task to not
complete. Pre-detection of an infinite loop condition is an example of when to use the FAILURE class of
assertions. Program execution is terminated.
Interactive debugging of a VHDL program is carried out entirely in the simulator in an environment
similar to graphical interface symbolic debuggers. The primary features of the simulator used for
debugging are:
- breakpoints: You can select any concurrent statement and ask the simulator to stop execution at
that point. Typically you would set a breakpoint on the process that is giving bad results.
- single step into: This allows you to step into a block of sequential statements such as a process
or function.
- single step over: This allows you to step over a block of sequential statements such as a function call
- step to event: Asks the simulator to continue execution of the program until the next event
(change) occurs on any signal.
- step to end: Continues execution until the end of the current time step.
Break points can be inserted by clicking on Source under View pull-down menu, then click on any
line numbers in the text window. A red dot will appear if a break point is successfully inserted at the line.
Step and Step Over are two buttons in the interface window.
Next: A VHDL example
Up: VHDL
Previous: Compilation and Simulation
Geun Rae Cho
Tue Aug 24 19:15:12 MDT 1999