VLSI System Design (EE 575)
Lab 1
 
Inverter/NAND/NOR

 

 

1. Objectives

The objective of this lab is to understand the basic cell design in VLSI. By using the SPICE model parameters, the relationship between the rise time and the fall time of a CMOS gate can be adjusted accordingly. In addition, by varying W/L ratios between the p-channel and the n-channel transistors in an inverter, the inverter’s threshold voltage, Vth, can also be adjusted.

2. Lab Description and Specs

Function:

Build in schematic and layout an inverter, 2-input NAND and 2-input NOR gates with balanced rise/fall time. Investigate varying ratios for different inverter threshold voltages.

Deliverables: Due by the beginning of Lab2

Schematics from DA for balanced inverter, NAND, and NOR showing proper sizing, valid instance names, correct model (ASIM_MODEL) properties.
Layout from ICstation for balanced inverter, NAND, and NOR.
Clean netlists (only useful comments) for all circuits (generated from DA and IC).
Output waveforms showing rise and fall time for the balanced inverter, NAND, and NOR (DA and IC).
Graph showing Vth as a function of Lp/Ln for the inverter.
Explain your overall workflow from start to finish.
Explain the process you used to balance your gates.
Explain the ratio you found balanced your inverter. Why is it what you found?
Explain how and why Vth varies with Ln/Lp.
Compare the rise and fall times of the schematic netlists to the layout netlists for all gates. If there is any difference, explain it.

3. Recommended Procedures For this lab you will lay out an inverter for balanced output and 4 more inverters for varying W/L ratios to determine the Vth characteristics of inverters implemented under the target processing technology. For those non-balanced inverters, make Wn = Wp = Wmin. Change the ratio Lp/Ln in a range between 0.1 to 10 with the sampling points equally spaced. The following lists the recommended steps:

Week 1:

  1. Use DesignArchitect to produce an inverter schematic. (instructions here)
  2. Export an Accusim viewpoint from DA.
  3. Generate a netlist from the schematic with Accusim. (instructions here)
  4. Edit and clean the netlist as needed to produce the different inverter configurations.
  5. Simulate the netlist in Esim to verify the balanced output and the varying Vth values.
    Plot the relationship between Vth and Lp/Ln ratio (see here for Vth info).
  6. Build (schematic and netlist) and simulation a NAND and NOR gates with the same rise and fall time of the balanced inverter.

Week 2:

  1. Use ICstation to layout the balanced inverter.
  2. Run DRC and ERC checks for the layout.
  3. Extract the netlist from the layout (clean the netlist).
  4. Simulate the netlist in Esim to verify the balanced output (and your layout).
  5. Repeat for NAND and NOR gates.