ELDO Sim Tutorial

 

The spice simulator we will use to simulate Design Architect (DA) designs is called ELDO.   ELDO is invoked by typing eldo <filename>, where filename is the file containing the netlist you wish to simulate.  Optional command line arguments can be found by typing eldo without specifying a filename.  If no extension is specified, ELDO’s default extension is .cir.  ELDO can also be run from the ESIM GUI, which is run by typing esim.  The ESIM GUI is preferred and is used in this tutorial.

 

Simulating A Sample Analog Design

 

  1. Complete analog design in DA.  See section 2.3 of Introduction to Mentor Graphics in the lecture notes.  Since we will be using ELDO instead of ACCUSIM there are several modifications to this section.
    1. In instruction twelve (12), the model property should be changed to pch.x (for P-type transistors) or nch.x (for N-type transistors).  The x is a number that depends on the length and width of the transistor and can be found in the 1.8V Mos Devices table. 
    2. In instruction thirteen (13), the INSTPAR property should be added to reflect the size of the transistors.  The form for this model is W=x.xU L=x.xU, where x.x is the size and the U specifies microns.
    3. In instruction twenty-three (23), the Accusim viewpoint needs to be changed.  The command should be changed to the following:  create_accusim_vpt –design <design_name> -model /class/EE571/models/log018.eldo53

 

  1. Once the design has been checked and saved, a netlist can be created using Accusim. 
    1. Type accusim <design_name> to begin.
    2. From the Report menu, choose Netlist, View Schematic Netlist.  Check to make sure your design’s devices are in the netlist.  Transistors start with m’s; resistors with r’s; capacitors with c’s, etc.
    3. If the devices are shown correctly in the netlist, choose Report, Netlist, Write Schematic Netlist.  Save the netlist with the filename <design_name>.cir.
    4. Exit Accusim. In the Exit Simview dialog, choose exit without saving.

 

  1. To run ELDO, type esim.
    1. First, use the text editor button to open your netlist (<design_name>.cir).  Click the diamond next to the TEXT EDITOR button and select your netlist file from the file navigator dialog box.
    2. In an ELDO Spice netlist, *’s denote comments.  Comment (or delete) the design line, the .op line and the V_Dcinit line.  Other commented lines can be deleted if it makes the file clearer. 
    3. Add this line somewhere near the top of the file: .LIB /class/EE571/models/log018.eldo53 TT.  The TT specifies the typical case parameters for the library file.
    4. Add electrical source definition lines as follows:

vo   GND   0    DC    0

vdd   VDD   GND   DC   1.8V

e.       Add an input waveform:  v1 in GND pwl(0 1.8 5n 1.8 5.01n 0) or v1 in GND pulse(0 1.8 0 100p 100p 5n 13n), where in is the name of the input node to your design.  Multiple lines can be added for multiple input circuits. The pwl defines a piecewise linear function, and the pulse defines a pulsed function.  Either can be used for a simulation.

f.        Add a transient analysis: .tran 0.001ns 10ns.  The first number specifies the step size for the simulator to use and the second number is the end time of the simulation.

g.       Add a plot:  .plot v(in) v(out). This will plot the voltage at nodes in and out from your design.

h.       Save the netlist file.  Run ELDO by clicking the diamond next to the ELDO button.  Select your netlist file from the file navigator dialog and click the ELDO button.  If there are no errors in the ELDO CONTROL dialog box, then the simulation ran successfully.

 

4.      Run XELGA to view the plot created from the simulation.

a.       Click the diamond next to the XELGA button.  Select the <design_name>.cou file and click the XELGA button to view the plot. 

b.      Select View, Zoom, Mouse to use the mouse to zoom in on an area of interest on the graph.

c.       Selecting Graph, Cursor, Set allows you to place a cursor on a waveform that will tell you the voltage level and time value. 

 

 

  1. Useful commands to define and view bus signals in ELDO:
    1. .SETBUS – The .SETBUS command creates a bus with bits defined from most to least significant.

Syntax:  .SETBUS bus_name Pn {Pn}

Example: .SETBUS A A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

creates a 16 bit bus called A with bits A15-A0

 

    1. .SIGBUS –  The .SIGBUS command sets the values of the bus.

Syntax:  .SIGBUS bus_name VHI = Val1 VLO = Val2 TFALL = Val3 TRISE = Val4 BASE = OCTAL | DEC | BIN | HEXA  Tn Val {Tn Val}

Example:  .SIGBUS A VHI = 1.8 VLO = 0 TRISE=0.2n TFALL=0.2n BASE=HEXA 0 0000 10n FFFF 15n 1234

sets the value of bus A  to hex 0 at 0, hex FFFF at 10n, etc, with a high voltage of 1.8V.  The VHI, VLO, TRISE, TFALL parameters are optional.

 

c.       .PLOTBUS  -- The .PLOTBUS command plots the signals belonging to a bus.

Syntax:  .PLOTBUS bus_name

The .PLOTBUS command will plot each signal in the bus.  The Page Composition menu option can be used to plot all of the signals on a single graph.

 

d.      .CHECKBUS – The .CHECKBUS command  can be used to compare the value of the the bus with the expected value.  NOTE: This command does NOT seem to be supported with Eldo version 5.3, the current version.

Syntax:  .CHECKBUS bus_name VTH=Val1 VTH2 = Val2 BASE = DEC | OCT | BIN | HEX Tn Val {Tn Val}

Example:  .CHECKBUS A VTH = 0.8 VTH2 = 1.0 BASE = HEXA 0n 0000 5n FFFF

The example checks that bus A has the hex value 0 at time 0 and the hex value FFFF at time 5n.  The value of the bus is set to be 1 if the voltage value is greater than VTH2 and O if less than VTH.  If only VTH is specified the value is 1 if the voltage is greater than VTH and 0 if the value is less than VTH.  If the .CHECKBUS command returns a result, the Eldo program dialogue states that there is a .CHECKBUS result.  The value that Eldo finds for the bus compared to the expected value is shown in the .chi file in this case.