THE CHALLENGE: You requested a transfer to Banana Electronics' fruitful R&D group, and got it.  A client has an OEM (Original Equipment Manufacturer) application for a adder/subtractor, and the  management has developed a plan to market a commercial adder/subtractor device.  Banana will produce these circuit boards after you develop the first prototypes. The specifications are given below.
Complete the schematic design of a 8-bit Adder/Subtractor with Full-adder as blocks as prelab. Also include design of the full-adder.

ADDER-SUBTRACTOR CIRCUIT: In this OEM application, A and B represent two eight-bit, two's complement numbers, [a7,a6,....a0] and  [b7,b6,... b0] (with a7, b7 being the most significant bits (MSB)). The output of the circuit consists of an 8-bit result S [s7,...s0], and a line 'OF' that is 1 when overflow occurs, and 0 when no overflow is involved.

NOTE: If you are using DE0 board, since it has fewer number of switches, you  should ground the last 4 bits of your both inputs and take the first four bits from the board switches. i.e. input A[a7,a6,a5,a4] will be grounded and A[a3,a2,a1,a0] will be assigned to switches on the board. Same is applicable to input B.

A control input 'Add/Sub' controls the operation as follows:
When  Add/Sub = 0, the units performs addition, i.e., S =  A + B.
When  Add/Sub = 1, the units performs subtraction, i.e., S = A - B.

Design Constraint: use only 2-input AND, OR, XOR  gates, and NOT gates, in your design.

Hint: Follow this procedure to proceed smoothly to your prototype . . .

• Write a truth table for Full Adder (FA).
• Simplify FA equations to SOP expressions and implement
  
• Design a bit-slice for the adder subtractor using one FA and additional gates as necessary
  
• Construct the 8-bit Adder/Subtractor circuit
  
• Lay out the circuit with Quartus II and produce a timing diagram. You will be reusing some of the components designed here, in future assignments. To facilitate this, layout a one bit slice of the circuit first and then assemble 8 of them to make the 8 bit adder.  Steps involved are as follows:
  
  • 1: Create a new project with the name "Lab4"
  • 2: Create a new Schematic Diagram & save it as "FA.bdf"
  • 3: Build your full adder using logic components. Name your inputs as X, Y, Ci and outputs as S, Co.
  • 4: Save the design
  • 5: Use File --> Create/Update --> Create Symbol File for Current File from the menu. This will create a block named FA for your full adder.
  • 6: Create another Schematic Diagram & save it as "Lab4.bdf".
    
  • 7: To add the newly created FA click on the Symbol tool. Then click on the + sign near the label "Project" from the Libraries: list. This will show you the FA.
  • 8: Add 8 FAs to your design. Then add necessary gates, inputs (a7...a0, b7...b0, Add/Sub), & outputs (OF,s7,...s0).
    
    
• Verify your implementation by applying 8 different input combinations, two of which should indicate overflow condition. Your report will include functional simulation timing diagrams for the  combinations that you tested.
• Implement your design on the DE board and demonstrate your design in hardware at the next group meeting.
• Test the circuit with the 8 input combinations that you used above.
  

REPORT

Prepare a Memorandum which is addressed to the manager of the R&D group at Banana. Go to the Preparing the Memo link to review the general requirements for Banana Memos or to the What to Include in Report #4 link for the specific things to include in the Project #4 report.

_______________