Project 3:
Design, Simulation and Verification of Combinational Circuits

Project Three asks you to simplify equations and design circuits using only AND, OR, and NOT gates.

You will also get introduced to the basics of Verilog in this lab.

You will submit a memorandum reporting your results. This memo should contain a few paragraphs of explanation, with several attachments. To do Project Three and prepare the report, choose any of the links below:

The Challenge
Why You Are Doing This Project
Prelab (Important - Complete before the lab)
Preparing the Memo
What to Include in Report and Grading Policy

Due date of report: Your report is due at your lab session one week after the Challenge was given.