Project 2:
Schematic Entry, Timing Diagrams and Functional Simulation using Quartus II

Project Two is aimed at entering a gate level design using Quartus II software, simulating to ensure that it functions correctly, implementing the circuit on the FPGA, and testing the circuit. You will further explore Quartus II software to be able to enter gate-level schematic designs, simulate the circuit for different input patterns and verify the circuit using timing diagrams. Like with the previous project, you will program the FPGA and verify the operation of the circuit.

As a Digital Logic Engineer, you will report your results in a memorandum to your supervisor at Banana Electronics.

To get technical details of your Challenge, technical background, write-up, etc., click on the appropriate link below. Note that this means that you will be following the Quartus II Tutorial from the link below. Use the example circuit in the tutorial for this lab.

The Challenge
Technical Background (Quartus II Tutorial from Altera DE0)
Why You Are Doing This Project
Prelab (Important - Complete before the lab and show it to your TA)
Preparing the Memo
What to Include in Report and Grading Policy

Due date of report: Your report is due at your lab session one week after the Challenge was given.

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