Digital Simulation

Because your design was created using the Xilinx library you first need to run the functional simulation.

1. In design manager, select the icon for your design then with the cursor positioned over the icon use the right mouse button to go to Open and 6 pld_men2xnf8. In the PLD XNF Translation window that opens set:

   Part Type: 4008epc84
   Run Memgen Only?: No
   Verbose Output?: No
   Help?: No
   

   Then click on OK.

2. Now, repeat the previous step but instead go to Open and 5 pld_fncsim8. A functional model is created for each component in the schematic. These functional models are used during functional simulation to specify the functionality of each component. If you select the option in the PLD Functional Simulation window to Run Quicksim?, the quicksim window will open after the functional simulation model is created.
3. If you want to add delay to the simulation, go to Open and pld_timsim8. Instead of obtaining a functional model like you did with pld_fncsim8, a set of timing models are generated by pld_timsim8 for simulation.
4. When Quicksim opens click on Open Sheet. You can select signals in the schematic then click on Trace to add them to view their wave forms.
5. Enter the command add tr //globalsetreset. This signal has to be pulsed high then low before your simulation will run.

Refer to the previous section on digital simulation for more details on using Quicksim.