Start From VHDL Model

VHDL model can be synthesized and mapped to Xilinx bit files using Leonardo on a PC.

1. set up PC environment
   1. push Start button
   2. select Settings and Control Panel
   3. double click System
   4. choose environment page tab
   5. in the user variables for <login nane>, click Path, and add and click set and Apply. type LM_LICENSE_FILE in the Variable field, and add 1700@hickory:2200@hickory, and click set and Apply. Click OK to finish.
2. launching Leonardo by pushing Start button and select Programs, Leonardo 4.2.2, and Leonardo.
3. now start compiling and synthesizing the VHDL model.
   1. click Flow Guide.. , and select Xilinx 4000E in the Target technology field,
   2. click Run Flow Guide
   3. in the Flow Guide window
      • click Load Library button, and select Xilinx 4000E in the popup menu and start loading.
      • click Load Modgen button, and select "Xilinx 4e" in the popup menu and start loading.
      • click Read button, and enter the VHDL source file name in the File Name field, highlight VHDL button, Do Auto .... button, and Xilinx, and click read
      • click Bubble Tristate button, and then click bubble_tristate button in the popup menu.
      • click Optimize button, and highlight Xilinx 4000E button, Remap button, Chip button, and Delay, and click optimize to start optimization.
      • click Write button, and enter the output edif file name in the name field and highlight EDIF, and Do Auto.... button.
4. launching Xilinx Design Manager by pushing Start button, and then select Programs, Xilinx, and Design Manager.
5. once inside, use the File pull-down menu to click on New Project.
6. use the browse button for input design to select the edif file you created in Leonardo. The work directory field should automatically be filled once the input design field is filled.
7. use the Design pull-down menu to click on Implement. In the Part field, make the following selection:
   Family : XC4000E
   Device : XC4008E
   Package: PC84
   Speed : -3
   The 7-segment display and LEDs on teh Xilinx board are connected to a set of output pins from the XC4000E chip. You can specify which output port in your VHDL model to which output pin on the chip that is connected to a specific LED or as part of the 7-segment display. The chip's pin numbers related to the LEDs and 7-segment displays is listed in the Xilinx board documentation. The required mappings are user constraints that can be defined in the model_name.ucf file. The format of the model_name.ucf file is
   net output_pin_name_in_VHDL LOC=Pxx;
   net output_pin_name_in_VHDL LOC=Pyy;
   where output_pin_name_in_VHDL is the output signal name in the VHDL model that you want to be mapped to an LED or a 7-segment display. Pxx and Pyy are the pin numbers associated with a specific LED or the 7-segment display. For example:
   net clear LOC=P20;
   net output<0> LOC=P61;
   Once the ucf file has been created, it can be specified by clicking the Options button on the Implement pop-up window. You only need to fill in the User Constraints field in the Options pop-up window with the path to the ucf file. Click the Run button in the Implement pop-up window. The Xilinx design compiler is now generating the bit-stream file for downloading to the Xilinx board.
8. once the bit-stream file is successfully generated, use the Tools pull-down menu to click on Hardware Debugger. Ignore the warning message.
9. make sure that Xilinx board is propoerly reset by pressing the reset button (SW4) and the prog. button (SW6) once.
10. once inside hardware debugger, highlight the bit-stream file icon (model_name.bit) and use the Download pull-down menu to click on Download Design. When the bit file is downloaded, you can see the live action on the board.