The Challenge
There are two parts in this lab assignment. The first part is to design, simulate and test an 8-bit parallel in parallel out right/left shift register using D flip flops. In the second part, you will design and test a register bank.
Part I:
A shift register allows the bits of its contents to be
moved to left or right. Shift registers can be used to convert
between serial and parallel interfaces, and for division or
multiplication by powers of two. In Part I, you are required to
design, simulate and test an 8-bit Parallel-in-Parallel-out
(PIPO) shift register using D Flip-Flops from the Quartus II
library.
In PIPO shift register, all the bits of data can be loaded at the same time. Also, all bits of shifted data can be read out at the same time. Four basic operations are required in this design. The First is maintaining the data already in the register. In this case output data is maintained and without any change. The second action is loading data, where the 8-bit input data is loaded into shift register. The third and fourth operations involve shifting data in right and left directions respectively with each clock that is applied. The MSB and LSB will have 0's shifted into their location. For example, if the input data is 00001110, the right shifted data outputs after 1, 2, 3 and 4 clocks are: 00000111, 00000011, 00000001, 00000000 respectively. The corresponding left shifted data outputs are : 00011100, 00111000, ... , 11100000, 11000000, 10000000, 00000000. The data is shifted until you change the operation. Figure 1 shows the block diagram of the 8-bit PIPO shift register:
Figure 1: Block diagram of 8-bit PIPO shift register.
In the design, switching among different operations can be done by using a multiplexer. One operation at a time will be selected by entering corresponding control bits to the MUXas summarized in Table 1.:
Table 1: Controlling inputs for MUX.
A 2-bit slice of the 8-bit PIPO shift register may be implemented as shown in Figure 2. When S1S0 = 11, output Q of D Flip-Flop is selected as input of D Flip-Flop by MUX so output data will remain the same. When S1S2 = 00, input bit I is selected by MUX to be loaded to D Flip-Flop. When S1S2 = 10, output Q from left side D Flip-Flop is selected as the input for current D flop-flip so that data bit is shifted in right direction. When S1S2 = 01, data bit is shifted in left direction.
Think about how the 2-bit slice will differ from the full 8-bit PIPO shift register. What values are selected as inputs to the D Flip-Flops for the MSB and LSB?
Figure 2. Part of PIPO shift register.
Let SW0-SW7 be the inputs, LEDR0-LEDR7 be the outputs, KEY0 be
the clock of D Flip-Flop, SW17 be the enable (INV) of MUX, SW16
be S1 and SW15 be S0. CLR (clear pin) for D Flip-Flop is KEY1.
The description of D Flip-Flop and 4:1MUX in Quartus II can be
found here (attachment).
Part II:
A register bank is a collection of registers with control
circuitry that allows data to be written to and read from
different registers. Large register banks are widely used in
microprocessors and other programmable devices. We will design a
register bank of three registers (R1, R2 and R3), a keypad for
input, and a display unit for output. Once the design is
complete, you will be able to transfer data entered on the
keypad to any register, transfer data from one register to the
other, and display the contents of any register.
Registers:
Rather than designing a register from flip-flops and other
components like in Part I, you will use 74173 register available
in Quartus library. 74173 is a widely used register, the data
sheet of which is available here [74173
Datasheet]. As reproduced in Figure below,
74173 is a 4-bit register with tri-state outputs.
Figure 3. Logic
diagram of 74173 Quad D flip-flop [Source: Motorola]
Note that holding control lines OE1 and OE2 LOW, causes
flip-flop contents to appear at the output while holding either
or both HIGH causes the output to be high-impedance. Input data
D0-D3 are latched to the register on the positive clock
edge provided both DE1 and DE2 are LOW. Thus you can
prevent data from being latched to the register by making one or
both of them HIGH.
What does it take to prevent input data D0-D4 from being
stored, or cause it to be stored when a clock is applied? What
does it take to cause the stored data to appear on Q0-Q4
or for Q0-Q4 to be high-impedance? Figure 4 gives the design for
an 8 bit register. Implement it and verify that you are
correct.
Figure 4. Circuit diagram for an
8-bit register using chips 74173
Register Bank:
Now you will design and implement a register bank consisting of
three 8-bit registers (R1,R2 and R3). The inputs and outputs of
the registers are connected to a Data Bus, which serves as both
an input data bus to write data to a selected register, and an
output data bus which carries the output of a selected register.
For example, if you enable the output of R1, contents of R1
appears on the data bus, and if you enable the input of R2
(while inputs of R1 and R3 are disabled) and apply a clock, data
in R1 now gets copied to R2. We can denote this operation R2
<-- R1. What does it take to do the operation R2 <-- data
from key pad or R3<--R1?
To prevent data from keypad appearing on the bus when that data
is supposed to come from a register, use it in conjunction with
a Tri-State Buffer Array (TSBA) as shown in Figures 5 and 6. A
TSBA (Figure 6) is used to allow or restrict data flow through a
data line/ bus. Note that the registers R1-R3 have built-in
TSBAs or both input and output.
If you treat the keypad as register R0 for identification and
control purposes, 2 bits will allow the selection of one of the
four units (Keypad, R1, R2 and R3).
Use a 2:4 decoder (Input_Register_Select) to
select the source of the data and another (Output_Register_Select)
to select the destination of the data.
Be sure to select decoders with appropriate polarity (active low
or active high outputs). Use 2 switches (In1,In0) and another
two (Out1,Out0) to set the values of Input_Register_Select
and Output_Register_Select respectively.
Figure 5. Schematic diagram of register bank
Figure 6. Keypad block diagram Figure 7. Tri-State Buffer Array
Instead of creating two 2:4 decoders, we will use the inbuilt 74139 2:4 decoder chip to create decoder control for "In" decoder and "Out" decoder shown in Figure 5. It has 2 decoders and selector pins to enable required decoders. The pin details are listed below:
A1, B1: decoder 1 inputs
A2, B2: decoder 2 inputs
Y10N.. Y13N: Decoder 1 outputs
Y20N.. Y23N: Decoder 2 outputs
G1N, G2N: Decoder selector
0 0 : Enables both decoder 1 and 2
0 1 : Enables decoder 1
1 0 : Enables decoder 2
1 1 : Disables both decoder 1 and decoder 2
Thus, the "decoderSelector[1..0]" pins will select decoder 1 with value '01' and decoder 2 with value '10'.
The connections for the decoder circuit are shown in Figure 8. The NOT gate on Y20N output will help to enable/ Disable the Keypad TSBA.
Figure 8: Decoder 1 and 2 with selector circuit
1. Pay attention to the polarity of signals when library cells are used. For example, in 74143, the enable signals are active low, i.e., enabling the circuit requires the values (DE1, DE2, OE1,OE2) to be low. In contrast, in Fig 6 and 7 enable signal is active high, i.e., TSBA is enabled when the value EN is high.
NOTE: Test each block individually and then integrate. Test each step during integration.
DEMO
Part 1: Pick an input number randomly and demonstrate
load, right shift and left shift functions of the shift
register. Then pick another input number and do the same.
Part 2: Demonstrate transfer of data from the
keypad to registers, and from one register to the other.
Your report will include functional simulation timing diagrams
for both shift Register and Register bank.
REPORT
Prepare a memorandum which is addressed to the manager of the
R&D group at Banana. Go to the Preparing the Memo link
to review the general requirements for Banana Memos or to the What to Include in Report #9
link for the specific things to include in the Project #9
report.