Technical Program List
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Monday August 3, 2015 (10:20 - 11:40)- Memristors (Room 300) [Chair: Onur Tigli, University of Miami]
- [1459] A Chaotic Attractor From a Memristor System - Field-Programmable Gate Array Realization and Rigorous Analysis
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- [1610] Memristor Emulator based on Practical Current Controlled Model
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- [1711] Investigating Power Characteristics of Memristor-based Logic Gates and Their Applications in a Security Primitive
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- [1792] A Reference-Less Multilevel Memristor Based RRAM Module
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- [1459] A Chaotic Attractor From a Memristor System - Field-Programmable Gate Array Realization and Rigorous Analysis
- Analog Circuits I (Room 304) [Chair: Chris Winstead, Utah State University]
- [1247] A 70°Phase Margin Differential OPAMP with Positive Feedback in Flexible a-IGZO TFT Technology
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- [1630] A Charge-Redistribution Based Controller for Keeping Charge Balance in Neural Stimulation
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- [1714] A Hardware Trojan Vulnerability in Inverse Widlar Reference Generator
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- [1873] A High Precision and High Speed Voltage-Mode Loser/Winner-Take-All Circuit
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- [1247] A 70°Phase Margin Differential OPAMP with Positive Feedback in Flexible a-IGZO TFT Technology
- Sensors (Room 308) [Chair: Vishal Saxena, Boise State University]
- [1037] On-Chip Digital Calibration for Automatic Input Impedance Boosting during Biopotential Measurements
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- [1306] Flexible PVDF Ferroelectric Capacitive Temperature Sensor
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- [1669] A Pseudo-Differential Charge Balanced Ratiometric Readout System for Capacitive Inertial Sensors
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- [1898] Biomedical Sensor Interface for PLI Cancellation
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- [1037] On-Chip Digital Calibration for Automatic Input Impedance Boosting during Biopotential Measurements
- RF Circuits I (Room 322) [Chair: Vassili Kireev, Xilinx Inc.]
- [1024] CMOS-MEMS Novel Resonator for Filter Tuning
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- [1558] A 8–14 GHz Varactorless Current Controlled LC Oscillator in 16nm CMOS Technology
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- [1725] A Low-Power Two-Stage Harmonic Rejection Quadrature Mixer Employing Bias-Current Reuse
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- [1891] A 100 Gb/s Transimpedance Amplifier with Diode-Connecting Input-Resistance-Reduction in 32nm CMOS Technology
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- [1024] CMOS-MEMS Novel Resonator for Filter Tuning
- Application of FPGA (Senate Chambers 204) [Chair: Eric Fetzer, Intel Corp.]
- [1744] An FPGA Based Passive K-Delta-1-Sigma Modulator
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- [1804] FPGA Design Space Exploration of IDEA Cryptography IP Core
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- [1871] Process Variation Immunity of Alternative 16nm HK/MG-based FPGA Logic Blocks
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- [1744] An FPGA Based Passive K-Delta-1-Sigma Modulator
- Student Papers I (Room 324) [Chair: Yong-bing Kim, Northeastern University]
- [1278] A 10-Gb/s Inductorless AGC Amplifier with 45-dB Linear Variable Gain Control in 0.13-um CMOS
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- [1718] A Delta-Sigma-Based Transmitter Utilizing FIR-Embedded Digital Power Amplifiers
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- [1889] Inductorless bandwidth extension using local positive feedback in inverter-based TIAs
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- [1921] Optimizing Power of Many-Core Systems by Exploiting Dynamic Voltage, Frequency and Core Scaling
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- [1278] A 10-Gb/s Inductorless AGC Amplifier with 45-dB Linear Variable Gain Control in 0.13-um CMOS
- Posters I (Ballrom C) [Chair: Jake Baker, University of Nevada, Las Vegas]
- [1027] Cascoded Power Stage With Automatic Dead Time Generation
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- [1171] Bioreactor Profile Design and Optimization For Ethanol Production
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- [1311] Cryptanalysis of a Double Scroll Based "True" Random Bit Generator
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- [1437] A Booth-Like Modulo operator
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- [1460] A Netlist Implementation of the Newton Fixed-point Homotopy Method for MOS Transistor Circuits
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- [1582] Low-power, serial interface for power-constrained devices
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- [1609] Comparative Analysis and Parameter Extraction Automation of Annular MOSFETs
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- [1731] Analyzing the Performance of a Configurable ROPUF Design Controlled by Programmable XOR Gates
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- [1783] Feedback Gain Phase Alignment Effects on Convergence Characteristics in Lucy-Richardson Deconvolution for Inversely Predicting Complex-Shaped RTN Distributions
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- [1786] Efficient Architecture and Implementation for NTRUEncrypt System
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- [1830] Switched-Compensation Technique in Switched-Capacitor Circuit for Achieving Fast Settling Performance
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- [1844] Reliable Gold Code Generators for GPS Receivers
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- [1946] Design and Implementation of an Embedded System for Monitoring At-home Solitary Alzheimer’s Patients
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- [1967] A Driver Circuit based on the emerging GaN-on-CMOS Process for the emerging Electroluminescent Panels
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- [1027] Cascoded Power Stage With Automatic Dead Time Generation
- Power Harvesting (Room 300) [Chair: Mahima Arrawatia, Indian Institute of Technology Bombay]
- [1116] Power Harvesting Using Tuned Comb Drive
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- [1565] Optimization of ON Current in Multilayer Molybdenum Disulfide (MoS2) based Tunnel Field Effect Transistor
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- [1687] An Active Rectifier with Optimal Flip Timing for the Internal Capacitor for Piezoelectric Vibration Energy Harvesting
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- [1698] A Battery-Less Power Management Circuit for RF Energy Harvesting with Input Voltage Regulation and Synchronous Rectification
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- [1116] Power Harvesting Using Tuned Comb Drive
- Digital Techniques I (Room 304) [Chair: Garrett Rose, University of Tennessee Knoxville]
- [1190] Differential Current-Mode Clock Distribution
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- [1329] A Process Tolerant Semi-Self Impedance Calibration Method for LPDDR4 Memory Controller
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- [1424] A Two-Dimensional Chaotic Logic Gate for Improved Computer Security
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- [1824] High Performance Single Supply CMOS Level Up/Down Shifter for Multiple Voltages
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- [1190] Differential Current-Mode Clock Distribution
- Biosensors I (Room 308) [Chair: Vishal Saxena, Boise State University]
- [1080] A Smart Transduction System with PVTA Compensation for Sensing Applications
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- [1129] A Wide Range and High Conversion Gain Power Detector for Frequency Shift Sensing Applications
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- [1892] A PVT-Compensated Capacitive Sensor with sub-1fF Sensitivity
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- [1894] A Single-Ended Chopper-Stabilized ISFET Amplifier for Continuous pH Measurement Applications
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- [1080] A Smart Transduction System with PVTA Compensation for Sensing Applications
- Special Session: Emerging Nanoelectronic Logic and Memory Devices based Circuits and Architectures (Room 322) [Chair: Rashmi Jha, University of Cincinnati]
- [1224] Current Voltage Characteristics of Partially Depleted Silicon on Ferroelectric Insulator Field Effect Transistor (PD-SOFFET)
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- [1498] Switching Characteristics Of MgO based Self-Compliant ReRAM Devices
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- [1936] Design of an MTJ-Based Nonvolatile Lookup Table Circuit Using an Energy-Efficient Single-Ended Logic-In-Memory Structure
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- [1963] Energy-Efficient Reconfigurable Computing Using Spintronic Memory
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- [1224] Current Voltage Characteristics of Partially Depleted Silicon on Ferroelectric Insulator Field Effect Transistor (PD-SOFFET)
- Amplifiers (Senate Chambers 204) [Chair: Chris Winstead, Utah State University]
- [1284] Switched-gain feedback amplifiers
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- [1318] Two-Phase Buck DC-AC Converter as Dynamic Power Supply for Amplitude-Modulated Class-DE Power Amplifier
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- [1705] Analysis of 1/f^2 and 1/f^3 Noise in the High-pass Chopper Amplifier with a High-Impedance Source
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- [1934] A CMOS ripple detector for integrated voltage regulator testing
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- [1284] Switched-gain feedback amplifiers
- Student Papers II (Room 324) [Chair: Yong-bing Kim, Northeastern University]
- [1447] A Perimeter Gated Single Photon Avalanche Diode Based Silicon Photomultiplier as Optical Detector
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- [1492] Fractionally Spaced Complex Sub-Nyquist Sampling for Multi-Gigabit 60GHz Wireless Communication
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- [1706] Exact and Approximated Discrete-Time Non-Linear Model of Voltage Switched CP-PLL
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- [1856] Exploiting State Obfuscation to Detect Hardware Trojans in NoC Network Interfaces
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- [1447] A Perimeter Gated Single Photon Avalanche Diode Based Silicon Photomultiplier as Optical Detector
- Power Management (Room 300) [Chair: Eric Fetzer, Intel Corp.]
- [1176] STG-based Detection of Power Virus Inputs in FSM
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- [1250] Electrical Circuit Modeling of A PEM Fuel Cell System Including Compressor Effect
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- [1273] Application of Used Electric Vehicle Batteries to Buffer Photovoltaic Output Transients
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- [1274] Buffer Sizing of Concentrated Photovoltaic Batteries: An Economic Analysis
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- [1176] STG-based Detection of Power Virus Inputs in FSM
- Digital Techniques II (Room 304) [Chair: Shaista Jabeen, North Dakota State University]
- [1220] A New Scalable Fault Tolerant Routing Algorithm for Networks-on-Chip
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- [1678] Scaled IIR Filter Based on Stochastic Computation
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- [1899] Runtime Slack-Deficit Detection for a Low-Voltage DCT Circuit
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- [1942] Revisiting Redundant Booth with Bias Multipliers
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- [1220] A New Scalable Fault Tolerant Routing Algorithm for Networks-on-Chip
- ADCs I (Room 308) [Chair: Chris Winstead, Utah State University]
- [1186] A 0.5V 11b Self-Calibrated SAR ADC
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- [1285] A 12-bit 20-MS/s SAR ADC with Improved Internal Clock Generator and SAR Controller
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- [1810] A 15.5-mW 20-GSps 4-Bit Charge-Steering Flash ADC
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- [1897] A 14-bit 200MS/s Low-Power Pipelined Flash-SAR ADC
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- [1186] A 0.5V 11b Self-Calibrated SAR ADC
- RF Circuits II (Room 322) [Chair: Jake Baker, University of Nevada, Las Vegas]
- [1164] A Blocker-Tolerant ZigBee Transceiver with On-Chip Balun and CR/IQ/IIP2 Self-Calibrations for Home Automation
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- [1264] Digital Cubic Interpolation and Synchronization for RF Receiver using Power-Gated ADC
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- [1501] Concurrent Dual-Band LNA For Automotive Application
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- [1932] A PA for MBOFDM-UWB and IR-UWB Transmitters
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- [1164] A Blocker-Tolerant ZigBee Transceiver with On-Chip Balun and CR/IQ/IIP2 Self-Calibrations for Home Automation
- Special Session: Silicon Photonics and Optical Transceivers I (Senate Chambers 204) [Chair: Cheng Li, Hewlett-Packard Labs]
- [1956] Silicon Mach-Zhender Interfermeter Modulator with PAM-4 data enconding scheme at 64 Gb/s
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- [1957] Energy Efficiency Comparisons of NRZ and PAM4 Modulation for Ring-Resonator-Based Silicon Photonic Links
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- [1959] High-speed Hybrid Silicon Microring Lasers
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- [1960] DWDM Nanophotonic Interconnects: Toward Terabit/s Chip-Scale Serial Link
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- [1956] Silicon Mach-Zhender Interfermeter Modulator with PAM-4 data enconding scheme at 64 Gb/s
- Converters I (Room 324) [Chair: Angsuman Roy, University of Nevada, Las Vegas]
- [1134] A Low-Power Hybrid ADC Architecture for High-Speed Medium-Resolution Applications
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- [1279] Digitally Programmable Offset Compensation of Comparators in Flash ADCs for Hybrid ADC Architectures
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- [1608] Voltage Source Based Voltage-to-Time Converter
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- [1944] A High-Accuracy Differential-Capacitance-to-Time Converter for Capacitive Sensors
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- [1134] A Low-Power Hybrid ADC Architecture for High-Speed Medium-Resolution Applications
- Digital Signal Processing I (Room 300) [Chair: Onur Tigli, University of Miami]
- [1232] High-speed multiplierless Frequency Response Masking (FRM) FIR filters with reduced usage of hardware resources
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- [1577] Using Cosine Filters to Improve Alias Rejection in Comb Decimation Filter
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- [1809] Design of IIR Digital Fractional-Order Differ-Integrators Using Closed-Form Discretization
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- [1232] High-speed multiplierless Frequency Response Masking (FRM) FIR filters with reduced usage of hardware resources
- Communication Circuits I (Room 304) [Chair: Tetsuya Shimamura, Saitama University]
- [1139] A High Precision Phase Control Unit for DDS-based PLLs for 2.4-GHz ISM band applications
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- [1213] MDLL/PLL dual path clock generator
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- [1328] IR-UWB BPK Transmitter Optimized for Maximum Distance of Transmission
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- [1139] A High Precision Phase Control Unit for DDS-based PLLs for 2.4-GHz ISM band applications
- Biosensors II (Room 308) [Chair: Michael Green, University of California, Irvine]
- [1551] Capacitive immunosensor for C-reactive protein quantification
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- [1886] CMOS Impedance Spectroscopy Sensor Array with Synchronous Voltage-to-Frequency Converters
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- [1922] A Low Power Frequency Synthesizer for Biosensor Applications in the MedRadio Band
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- [1551] Capacitive immunosensor for C-reactive protein quantification
- Wireless Systems (Room 322) [Chair: Juan Montiel-Nelson, University of Las Palmas de Gran Canaria]
- [1214] High Efficiency Delta-Sigma Transmitter Architecture with Gate Bias Modulation for Wireless Applications
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- [1776] TOWARD FAST LOW POWER ADAPTIVE SPIKE SORTING VLSI CHIP DESIGN FOR WIRELESS BCI IMPLANTS
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- [1866] Asynchronous Communication for Wireless Sensors Using Ultra Wideband Impulse Radio
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- [1214] High Efficiency Delta-Sigma Transmitter Architecture with Gate Bias Modulation for Wireless Applications
- Special Session: Silicon Photonics and Optical Transceivers II (Senate Chambers 204) [Chair: Cheng Li, Hewlett-Packard Labs]
- [1949] A Comprehensive Design Approach for a MZM Based PAM-4 Silicon Photonic Transmitter
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- [1955] Adaptively-Tunable RF Photonic Filters
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- [1958] 56 Gb/s PAM-4 Optical Receiver Frontend in an Advanced FinFET Process
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- [1949] A Comprehensive Design Approach for a MZM Based PAM-4 Silicon Photonic Transmitter
- Power Electronics (Room 300) [Chair: Igor Filanovsky, University of Alberta]
- [1026] An Asymmetric VHF Self-Oscillating DC-DC Converter with Integrated Transformer
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- [1674] A Robust Cross-Regulation-Suppressed Single-Inductor Multiple-Output DC-DC Converter with Duty-Regulated Comparator Control
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- [1893] The Complete Model of High Efficient Drive System for Electric Vehicles
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- [1026] An Asymmetric VHF Self-Oscillating DC-DC Converter with Integrated Transformer
- Communication Circuits II (Room 304) [Chair: Ioana Triandaf, United States Naval Research Laboratory]
- [1089] Hysteresis-Induced Chaotic Dynamics in a Transmission Line Model
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- [1215] Optimization of Antenna Beam pattern in Ad Hoc Networks for Optimal Global Performance
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- [1784] Utilization of Exponentiated Amplitude Spectrum for Speech Enhancement in Highly Noisy Environments
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- [1089] Hysteresis-Induced Chaotic Dynamics in a Transmission Line Model
- Optical Biosensors (Room 308) [Chair: Ana Gabriela Correa Mena, National Institute of Astrophysics, Optics and Electronics]
- [1448] Silicate Overcoat Layers for the Improvement of PECVD SiO2 Optofluidic Waveguides
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- [1450] Materials and Microfabrication Processes for ARROW-based Optofluidic Biosensors
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- [1880] Measuring Arc Dynamics Using a Slab Coupled Optical Sensor
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- [1448] Silicate Overcoat Layers for the Improvement of PECVD SiO2 Optofluidic Waveguides
- Packaging (Room 322) [Chair: Juan Montiel-Nelson, University of Las Palmas de Gran Canaria]
- [1310] Contactless Detection of Faulty TSV in 3D IC via Capacitive Coupling
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- [1384] A Contactless Testing Methodology for Pre-bond Interposer
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- [1787] Design of Compact Packaged Switched Reconfigurable Multi-Band BPF Using LTCC Technology
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- [1310] Contactless Detection of Faulty TSV in 3D IC via Capacitive Coupling
- Image Processing I (Senate Chambers 204) [Chair: Peter Stubberud, UNLV]
- [1309] A new image stream encryption technique
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- [1581] FPGA Emulation of a Spike-Based, Stochastic System for Real-time Image Dewarping
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- [1790] A Global Human Action, Facial and Gestures Recognition Algorithm Employing Multiple Features Extraction and CCA Classification
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- [1309] A new image stream encryption technique
- Posters II (Ballrom C) [Chair: Jake Baker, University of Nevada, Las Vegas]
- [1019] Concise Thermal to Electrical Parameters Extraction of Thermoelectric Generator for Spice Modeling
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- [1020] Improved SPICE Modeling and Analysis of a Thermoelectric Module
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- [1457] Supervised Facial Recognition Based on Eigenanalysis of Multiresolution and Independent Features
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- [1602] A Design Flow To Quantify And Limit Multiple Patterning Effects
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- [1648] Efficient Design Methodology for Application Specific Integrated Algorithm Systems (ASIAS)
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- [1691] Proposal of LED-based Peeping Prevention System
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- [1696] A One Zener Diode, One Memristor Crossbar Architecture for a Write-Time-Based PUF
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- [1702] Window Length Effect on Cross Frequency Coupling in an EEG Processing Circuit
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- [1788] Delta DICE: A Double Node Upset Resilient Latch
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- [1820] UEFI USB Bus Initialization Verification Using Colored Petri Nets
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- [1863] Particle Trapping in Electrostatically Actuated Nanofluidic Barriers
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- [1901] Effect of Flicker Noise on SEIR for Accurate ADC Linearity Testing
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- [1941] Microcontroller-based Electrochemical Impedance Spectroscopy for Wearable Health Monitoring Systems
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- [1019] Concise Thermal to Electrical Parameters Extraction of Thermoelectric Generator for Spice Modeling
- Digital Signal Processing II (Room 300) [Chair: Peter Stubberud, UNLV]
- [1049] Reduced-Latency Architecture for Image Smoothing Exponential Filters
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- [1248] Characterization of RNS Multiply-Add Units for Power Efficient DSP
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- [1568] Performance of Multi-Parents Genetic Algorithms (MPGA) for IIR Adaptive System Identification
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- [1812] Real-Time VLSI Architecture for Palm Rejection Using Wronskian Determinant
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- [1049] Reduced-Latency Architecture for Image Smoothing Exponential Filters
- Optics (Room 304) [Chair: Mohammad Sayeh, Southern Illinois University]
- [1355] Generation and Distribution of Microwave Signals by using Optoelectronic Oscillators
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- [1712] Rubidium Diffusion in Microscale Spectroscopy and Slow Light Platforms
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- [1817] Design and Fabrication of a Color Multiplexing LiNbO3 Device
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- [1923] High-Speed Graphene Based Quantum-Optical Interconnect Design
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- [1355] Generation and Distribution of Microwave Signals by using Optoelectronic Oscillators
- Bio Systems (Room 308) [Chair: Vishal Saxena, Boise State University]
- [1559] Design of a Biofeedback Device for Gait Rehabilitation in Post-Stroke Patients
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- [1617] Single Ion Channel CMOS electrochemical instrument for high throughput recording arrays
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- [1760] A Real-time and Portable Sign Language Translation System
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- [1966] A Novel Normalization Technique for Multimodal Biometric Systems
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- [1559] Design of a Biofeedback Device for Gait Rehabilitation in Post-Stroke Patients
- Analog Circuits II (Room 322) [Chair: Paul Furth, New Mexico State University]
- [1298] Analog Circuit Performance Bound Estimation Based on Extreme Value Theory
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- [1313] Translinear Circuit for 2-D Analog Error Correction
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- [1432] Chopper Stabilized Sub 1V Reference Voltage in 65nm CMOS
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- [1943] A Voltage Buffer Compensation Using a Flipped Voltage Follower in a Two-Stage CMOS Op-amp
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- [1298] Analog Circuit Performance Bound Estimation Based on Extreme Value Theory
- Σ - Δ Techniques (Senate Chambers 204) [Chair: Onur Tigli, University of Miami]
- [1077] On the Use of Passive Circuits to Implement LC-based Band-Pass CT Sigma-Delta Modulators
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- [1261] A 150 MHz Bandwidth Continuous-Time ΔΣ Modulator in 28 nm CMOS with DAC Calibration
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- [1423] Automatic filter calibration for tunable bandpass delta-sigma modulators
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- [1802] DAC Mismatch Shaping for Quadrature Sigma-Delta Data Converters
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- [1077] On the Use of Passive Circuits to Implement LC-based Band-Pass CT Sigma-Delta Modulators
- Power Amplifiers (Room 300) [Chair: Paul Furth, New Mexico State University]
- [1347] On-Chip Input and Ground Ringing Suppression in High-Frequency Buck Converters
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- [1412] A CMOS Power Amplifier with 180° Hybrid On-Chip Coupler for 4G Applications
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- [1785] A Quadband Concurrent Linear/Efficient Power Amplifier for Multiband Wireless Applications
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- [1948] Novel Single-Input Single-Output Two-Box Polar Behavioral Model for Envelope Tracking Power Amplifiers
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- [1347] On-Chip Input and Ground Ringing Suppression in High-Frequency Buck Converters
- ADCs II (Room 304) [Chair: Allen Waters, Oregon State University]
- [1029] A Digital Calibration Technique for Folding-Integration/Cyclic Cascaded ADC
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- [1428] Simplified Volterra Series Based Background Calibration for High Speed High Resolution Pipelined ADCs
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- [1816] Practical Modeling of Comparator Metastability for Conventional and LSB-first SAR ADCs
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- [1938] A Simple Ramp Generator with Level Spreading for SEIR ADC BIST Circuit
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- [1029] A Digital Calibration Technique for Folding-Integration/Cyclic Cascaded ADC
- Photonics (Room 308) [Chair: Aaron Hawkins, Brigham Young University]
- [1023] System parameter analysis on devices with Bi-stable characteristics
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- [1430] An optical clock receiver based on an injection locked ring oscillator featuring auto-calibration
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- [1875] High Voltage Measurements Using Slab Coupled Optical Sensors (SCOS)
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- [1023] System parameter analysis on devices with Bi-stable characteristics
- Special Session: Network on Chip (Room 322) [Chair: Sudeep Pasricha, Colorado State University]
- [1160] Improving Crosstalk Resilience with Wavelength Spacing in Photonic Crossbar-based Network-on-Chip Architectures
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- [1919] Energy-Efficient NoC with Variable Channel Width
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- [1951] Improving EDP in Wireless NoC-Enabled Multicore Chips via DVFS Pruning
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- [1952] Cyber-Physical Systems for Personalized and Precise Medicine
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- [1160] Improving Crosstalk Resilience with Wavelength Spacing in Photonic Crossbar-based Network-on-Chip Architectures
- Equalizers (Senate Chambers 204) [Chair: Samuel Palermo, Texas A&M University]
- [1130] An Input Pole Tuned Switching Equalization Scheme for High-speed Serial Links
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- [1195] A 40Gb/s 39mW 3-tap Adaptive Decision Feedback Equalizer in 65nm CMOS
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- [1349] A 10-Gb/s Receiver with a Continuous-Time Linear Equalizer and 1-Tap Decision-Feedback Equalizer
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- [1561] An 8Gbps Discrete Time Linear Equalizer in 40nm CMOS Technology
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- [1130] An Input Pole Tuned Switching Equalization Scheme for High-speed Serial Links
- Ocsillators (Room 300) [Chair: Marvin Onabajo, Northeastern University]
- [1010] Phase Calibration in Mutual Injection-Pulled Quadrature Oscillators
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- [1044] A Low-Power Temperature-Compensated Relaxation Oscillator for Built-in Test Signal Generation
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- [1112] Compensation for Imperfect Switching in a Chaotic Hybrid Oscillator Circuit
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- [1867] A 1.1-8.2 GHz tuning range In-phase and Quadrature output DCO design in 90 nm CMOS technology
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- [1010] Phase Calibration in Mutual Injection-Pulled Quadrature Oscillators
- PLLs (Room 304) [Chair: Juan Montiel-Nelson, University of Las Palmas de Gran Canaria]
- [1185] A Phase-Error Cancellation Technique for Fast-Lock PLL
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- [1520] Bitwidth-Aware Register Allocation and Binding for Clock Period Minimization
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- [1552] Modeling and Design of a 0.8-30 GHz Tunable Inductor-less Divide-by-2 Frequency Divider with Digital Frequency Calibration
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- [1822] A wide frequency range series-parallel coupled quadrature phase injection locked frequency divider
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- [1826] A Precise 360-Range Phase Detector for fdNIRS Application Using a Pair of XNORs
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- [1185] A Phase-Error Cancellation Technique for Fast-Lock PLL
- Nano Devices (Room 308) [Chair: Onur Tigli, University of Miami]
- [1111] Analytical Analysis of the Contact Resistance (Rc) of Metal-MoS2 Interface
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- [1144] Novel charge pump converter with Tunnel FET devices for ultra-low power energy harvesting sources
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- [1167] New Three Dimensional Doping Profile for Devices in Subthreshold Circuit
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- [1570] Subthreshold Swing Characteristics of Multilayer MoS2 Tunnel FET
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- [1962] Spintronics for Associative Computation and Hardware Security
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- [1111] Analytical Analysis of the Contact Resistance (Rc) of Metal-MoS2 Interface
- Processor and Memory Design (Room 322) [Chair: Justin Aguilar, Intel Corp.]
- [1187] Design and Implementation of Area Efficient Multiported Memories with Write Conflict Resolution
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- [1500] Single-ended 6T Sub-threshold SRAM with Horizontal Local Bit-Lines
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- [1679] Process Variation Aware Dynamic Power Management in Multicore Systems with Extended Range Voltage/Frequency Scaling
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- [1015] Physical Design and Implementation of POWER8™ (P8) Server Class Processor
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- [1187] Design and Implementation of Area Efficient Multiported Memories with Write Conflict Resolution
- Image Processing II (Senate Chambers 204) [Chair: Wasfy Mikhael, University of Central Florida]
- [1180] High-Throughput Hardware Implementation for Motion Estimation in HEVC Encoder
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- [1713] Multi-Feature Criteria with Fuzzy Logic Pattern Recognition for Hand Gesture Classification
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- [1815] Improving Video-Based Resting Heart Rate Estimation: A Comparison of Two Methods
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- [1884] Facial Recognition Employing Transform Domain Mutual Principal Component Analysis
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- [1180] High-Throughput Hardware Implementation for Motion Estimation in HEVC Encoder
- Special Session: Circuits for Enhancing Access to Radio Spectrum (EARS) and Phased-Array Radar (Room 300) [Chair: Nilan Udayanga, University of Akron]
- [1243] Tunable N-Path RF Front-end Filter with an Adaptive Integrated Notch for FDD/Co-Existence
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- [1680] A 24-GHz Low-cost Continuous Beam Steering Phased Array for Indoor Smart Radar
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- [1849] FPGA-based Network-Resonance Applebaum Adaptive Arrays for Directional Spectrum Sensing
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- [1850] Architecture Comparison for Concurrent Multi-Band Linear Power Amplifiers
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- [1243] Tunable N-Path RF Front-end Filter with an Adaptive Integrated Notch for FDD/Co-Existence
- Hardware Vulnerability (Room 304) [Chair: Falah Awwad, United Arab Emirates University]
- [1616] Assessment of NAND Based Ring Oscillator for Hardware Trojan Detection
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- [1724] A Slew Rate Enhancement Technique for Fully Differential Amplifier Without Inducing Trojan State
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- [1798] Tenacious Hardware Trojans Due to High Temperature in Middle Tiers of 3-D ICs
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- [1808] Hardware Tojans in Asynchronous FIFO-Buffers: From Clock Domain Crossing Perspective
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- [1616] Assessment of NAND Based Ring Oscillator for Hardware Trojan Detection
- Analog Filters (Room 308) [Chair: Wei Tang, New Mexico State University]
- [1445] Derivative-Free Active-RC Elliptic Filter Using Cascade of Biquads in 28 nm CMOS
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- [1860] Analysis of Discrete-Time Charge-Domain Complex Bandpass Filter with Accurately Tunable Center Frequency
Authors:
- [1926] Implementing S-Transform in Continuous-Time Using Non Linear Sequence Transformation
Authors:
- [1927] A Delta Sigma Based Finite Impulse Response Filter for EEG Signal Processing
Authors:
- [1445] Derivative-Free Active-RC Elliptic Filter Using Cascade of Biquads in 28 nm CMOS
- Converters II (Room 322) [Chair: Igor Filanovsky, University of Alberta]
- [1578] An Area Efficient 10-bit Time Mode Hybrid DAC With Current Settling Error Compensation
Authors:
- [1642] 0.25-4 ns 185 MS/s 4-bit Pulse-Shrinking Time-to-Digital Converter in 130 nm CMOS Using a 2-Step Conversion Scheme
Authors:
- [1646] A 12.88 MS/s 0.28 pJ/conv.step 8-bit Stage-Interleaved Pulse-Shrinking Time-to-Digital Converter in 130 nm CMOS
Authors:
- [1832] Overload Analysis of Continuous Time Sigma Delta Modulators
Authors:
- [1578] An Area Efficient 10-bit Time Mode Hybrid DAC With Current Settling Error Compensation
- Image Processing III (Senate Chambers 204) [Chair: Jake Baker, University of Nevada, Las Vegas]
- [1387] Pixel Truncation based on a Statistical Analysis for Low Power Block Matching
Authors:
- [1621] Robust Fabric Defect Detection Algorithm Using Entropy Filtering and Minimum Error Thresholding
Authors:
- [1765] Perception-based Video Coding with Human Faces Detection and Enhancement in H.264/AVC Systems
Authors:
- [1872] Surface-Based Morphometric Analysis of Hippocampal Subfields in Mild Cognitive Impairment and Alzheimer's Disease
Authors:
- [1387] Pixel Truncation based on a Statistical Analysis for Low Power Block Matching
Welcome from Memorial Reception Host: |
Prof. Ken Jenkins, School of Electrical Engineering and Computer Science, Pennsylvania State University |
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Location: | Scott Bioengineering Building |
Date & Time: | August 2, 2015 (18:30- 20:00) |
Five-minute Video Presentation
Memorial Speakers:
1. Prof. Hossein Hashemi, Ming Hsieh Department of Electrical Engineering - Electrophysics, USC
2. Emeritus Prof. Igor Filanovsky, Department of Electrical and Computer Engineering, University of Alberta
3. Prof. Jose Silva-Martinez, Department of Electrical and Computer Engineering, Texas A&M University
4. Prof. Magdy Bayoumi, Department of Computer Science, University of Louisiana at Lafayette
5. Prof. Sherif Michael, Department of Electrical and Computer Engineering, Naval Postgradaute School
Invited Talk: | The Science of Brewing Beer |
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Speaker: | Tony Rau, Odell Brewing |
Location: | Ballrooms C & D |
Date & Time: | August 4, 2015 (18:30 - 22:00) |
Tony Rau is the lab manager at Odell Brewing Company. He started out homebrewing in college and fell in love with craft beer. While pursing a degree in biochemistry at CSU, he started interning in the brewhouse for Odell and worked his way into the lab after graduating. One of his main job functions is managing the yeast for the brewery as well as growing bacteria for special projects and sours. He also has helped with recipe development for a couple of beers as well as being a member of the Quality Assurance team.