Dr. Thomas Wei Chen
Publications
Go To: Books Refereed Journal Articles Refereed Chapters Refereed Proceedings Non–Refereed Journal Articles
| books | Top | |
| 1 | "Application of Genetic Learning to Pass-Transistor Logic Design and Optimization" in Recent Advances in Simulated Evolution and Learning, Edited by Kay Chen Tan, Meng Hiot Lim, Xin Yao and Lipo Wang, World Scientific series on "Advances in Natural Computation," 2003. | 2003 |
| Refereed Journal Articles | Top | |
| 29 | W. Pettine, M. Jibson, T. Chen, S. Tobet, C. Henry, “Charaterization of novel microelectrode geometries for detection of neurotransmitters”, IEEE Sensors Journal, Vol. PP, Issue. 99, August, 2011. | 2011 |
| 28 | C. Thangaraj, R. Pownall, G. Yuanb, P. Nikkel, K. Kear, and T. Chen, Fully CMOS- Compatible On-Chip Optical Clock Distribution and Recovery", IEEE Trans. on VLSI Systems, Vol. 18, No. 10, 2010. | 2010 |
| 27 | R. Pownall, C. Thangaraj, G. Yuanb, P. Nikkel, T. Chen, and K. Lear, CMOS opto- electronic components for clock distribution", Microelectronic Engineering, Accepted for publication, 2010. | 2010 |
| 26 | C. Thangaraj, C. Alkan, T. Chen, “Rapid Design Space Exploration Using Legacy Design Data And Technology Scaling Trend Integration”, The VLSI Journal, Vol. 43, Issue 2, April 2010. | 2010 |
| 25 | J. Gregg and T. Chen, "Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well Adaptive Body Biasing (IWABB),"IEEE Trans. on VLSI Systems, Vol. 15, No. 3, pp.366-376, March 2007. | 2007 |
| 24 | R. Pownall, G. Yuan, T.W. Chen, P. Nikkel, and K.L. Lear, "Geometry Dependence of CMOS Compatible, Polysilicon, Leaky-Mode Photodetectors", accepted for publication in IEEE Photonics Technology Newsletters, Volume 19, Issue 7, April 2007. | 2007 |
| 23 | J. Kim and T. Chen, "A VLSI Architecture for Video-Object Segmentation," IEEE Trans. on Circuits and Systems for Video Technology (CSVT), Vol. 13, No. 1, pp. 83-96, January 2003 | 2003 |
| 22 | T. Chen, A. Bai, A. Hajjar, A. von Mayrhauser, and C. Anderson, "Fast Antirandom (FAR) Test Generation to Improve the Quality of Behavioral Model Verification," Journal of Electronic Testing: Theory and Applications (JETTA), Kluwer Academic Publishing, Vol. 18, No. 6, pp. 583-594, December 2002. | 2002 |
| 21 | J. Kim and T. Chen, "Multiple Feature Clustering for Image Sequence Segmentation," Pattern Recognition Letters, Elsvier Science B.V., Vol. 22, pp. 1207-1217, July 2001. | 2001 |
| 20 | G. Cho and T. Chen, "On Mixed PTL/Static Logic for Low-Power and High-Speed Circuits," VLSI Design: In International Journal of Custom-Chip Design, Simulation and Testing, Vol. 12, No. 3, pp. 399-406, July 2001. | 2001 |
| 19 | F. Alzaharani and T. Chen, "On-Chip TEC-QED Code for Ultra-Large, Single-Chip Memory Systems," International Journal of Computers and Electrical Engineering, Vol. 26, No. 6, pp. 317-335, December 2000. | 2000 |
| 18 | V.K. Kim and T. Chen, "On Comparing Functional Fault Coverage and Defect Coverage for Memory Testing," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 11, pp. 1672-1683, November 1999. | 1999 |
| 17 | T. Chen, V.K. Kim, and M. Tegethoff, "IC Manufacturing Test Cost Estimation at Early Stages of the Design Cycle," Microelectronics Journal, Elsevier Science, Vol. 30, No. 8, pp. 733-738, August 1999. | 1999 |
| 16 | T. Chen, V.K. Kim, and M. Tegethoff, "IC Yield Estimation at Early Stages of the Design Cycle," Microelectronics Journal, Elsevier Science, Vol. 30, No. 8, pp. 725-732, August 1999. | 1999 |
| 15 | G. Sunada, T. Chen, and Jian Jin "COBRA: a 100 MOPS Single-Chip Programmable and Expandable FFT," IEEE Trans. on VLSI Systems, Vol. 7, No. 2, pp. 174-182, June 1999. | 1999 |
| 14 | A. Hajjar and T. Chen, "A VLSI Architecture for Real-Time Edge Linking," IEEE Trans. on Pattern Analysis and Machine Intelligence, Vol. 21, No. 1, pp. 89-94, January 1999. | 1999 |
| 13 | M. Schaffer and T. Chen, "A Tree Matching Algorithm and VLSI Architecture for Real-Time 2D Object Classification" Journal Real-Time Imaging, Elsevier Science Publisher, Academic Press, Vol. 4, No. 3, pp. 193-202, June 1998. | 1998 |
| 12 | M. Tegethoff and T. Chen, "Simulation Techniques for the Manufacturing Test of Boards and MCMs," Journal of Electronic Testing: Theory and Applications (JETTA), Kluwer Academic Publishing, Vol. 10, No. 1/2, pp. 137-149, February 1997. | 1997 |
| 11 | F. Alzahrani and T. Chen, "A Real-Time Edge Detector: Algorithm and VLSI Architecture" Journal of Real-Time Imaging, special issue on Special-Purpose Architectures for Real-Time Imaging," Elsevier Science Publisher, Vol. 3, No. 5, pp.363-378, November 1997. | 1997 |
| 10 | M. Tegethoff and T. Chen, "Sensitivity Analysis of Critical Parameters in Board Test," IEEE Design & Test of Computers, Vol. 13, No. 1, pp. 58-63, January 1996. | 1996 |
| 9 | M. Tegethoff and T. Chen, "A Clustered Yield Model for SMT Boards and MCMs," IEEE Trans. on Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, Vol. 18, No. 4, pp. 640-643, November 1995. | 1995 |
| 8 | X. Wang and T. Chen, "On Performance and Area Optimization of VLSI Systems." VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing, Vol. 3, No. 1, pp. 43-51, January 1995. | 1995 |
| 7 | T. Chen and L. Zhu, "An Expandable Column FFT Architecture Using Circuit Switching Networks," The Journal of VLSI Signal Processing. Vol. 6, No. 5, pp. 243-257, May 1993. | 1993 |
| 6 | T. Chen and G. Sunada, "Design of A Self-Testing and Self-Repairing Structure for Highly Hierarchical Ultra-Large Capacity Memory Chips," IEEE Trans. on VLSI Systems, Vol. 1, No. 2, pp. 88-97, June 1993. | 1993 |
| 5 | T. Chen, "From System Design to IC Design in 14 Weeks - Teamwork Makes It Possible," IEEE Trans. on Education, Vol. 36, No. 1, pp. 137-140, February 1993. | 1993 |
| 4 | T. Chen, J. Mavor, P.B. Denyer, D. Renshaw, "A Traffic Routing Algorithm for Serial Superchip System Customization," IEE Proceedings, Part E, Computers and Digital Techniques, Vol. 137, No. 1, pp. 65-73, January 1990. | 1990 |
| 3 | T. Chen, J. Mavor, P.B. Denyer, D. Renshaw, "Yield Estimation for the Serial Superchip," IEE Proceedings, Part E, Computers and Digital Techniques, Vol. 136, No. 3, pp. 187-196, May 1989. | 1989 |
| 2 | T. Chen, J. Mavor, P.B. Denyer, D. Renshaw, "A WSI Approach Towards Defect/Fault-tolerant Reconfigurable Serial Systems," IEEE Journal of Solid-State Circuits, Vol. 23, No. 6, pp. 639-646, June 1988. | 1988 |
| 1 | T. Chen, J. Mavor, P.B. Denyer, D. Renshaw, "A Superchip Architecture for Implementing Large Integrated Systems," IEE Proceedings Part E, Computers and Digital Techniques, Vol. 135, No. 3, pp. 137-150, May 1988. | 1988 |
| Refereed Chapters in Books | Top | |
| 3 | Chapter 2, "Integrated Circuits," in Microelectronics, Edited by Jerry C. Whitaker, CRC Press. 2000. | 2000 |
| 2 | "On the Promise of Neural Networks to Support Software Testing," in Computational Intelligence in Software Engineering, Edited by W. Pedrycz and J.F. Peters, World Scientific Publisher, 1998. | 1998 |
| 1 | Chapter 45, "Integrated Circuits," in The Electronics Handbook, Edited by J. C. Whitaker, CRC Press. 1997. | 1997 |
| Refereed Conference Proceedings | Top | |
| 10 | Charles Thangaraj and Tom Chen, "Design Target Exploration for Meeting-Time-to-Market Using Pareto Analysis," IEEE International Symposium on Circuits and Systems, Seattle, Washington, USA, May 18-21, 2008 | 2008 |
| 9 | Charles Thangaraj and Tom Chen, "Early Design Phase Power Performance Trade-offs Using In-situ Macro Models," 4th IEEE International Symposium on Electronic Design, Tests & Applications, Hong Kong January 23-25, 2008. | 2008 |
| 8 | T. Wu, C. Alkan, and T. Chen, "Analysis and Improvement of SER Immunity of Combinational Logic", 16th IFIP/IEEE Int. Conf. on VLSI (VLSI-SOC 2008), Rhodes Island, Greece, Oct. 13 -- 15, 2008. (published) | 2008 |
| 7 | C. Thangaraj, T. Chen, "A Fully CMOS-Compatible Optical H-Tree & Clock Recovery System", 16th IFIP/IEEE Int. Conf. on VLSI (VLSI-SOC 2008), Rhodes Island, Greece, Oct. 13 -- 15, 2008. (published) | 2008 |
| 6 | T. Wu, A. Cengiz, T. Chen, "Improving SER Immunity of Combinational Logic Using Combinations of Spatial and Temporal Checking", 11th Euromicro Conference on Digital System Design, Parma, Italy, 2 -- 5 September 2008. (published) | 2008 |
| 5 | C. Thangaraj and T. Chen, "Design Target Exploration for Meeting Time-to-Market Using Pareto Analysis", IEEE International Symposium on Circuits and Systems, Seattle, Washington, USA, 18 -- 21 May 2008. (published) | 2008 |
| 4 | C. Thangaraj and T. Chen, "Early Design Phase Power Performance Trade-offs Using In-situ Macro Models", 4th IEEE International Symposium on Electronic Design, Test & Applications, Hong Kong, January 23 -- 25, 2008. (published) | 2008 |
| 3 | K.L. Lear, G.Yuan, M.D. Stephens, X.He, R. Pownall, R. Yan, P. Nikkel, C.S. Henry, T.W. Chen, and D.S. Dandy, "A Waveguide Biosensors Local Ecanescent Field Response to an Immunoassay Complete", IEEE LEOS Summer Topical Meetings/Biophotonics, paper TuB2.2,Portland, Oregon, July 24,2007. | 2007 |
| 2 | C.V. Tangaraj and T. Chen, "Power and Performance Analysis for Early Design Space Exploration," Proc of IEEE Computer Society Symposium on VLSI, Porte Alegre, Brazil, June 9-11, 2007. | 2007 |
| 1 | C.V. Tangaraj,K.Stephenson,T. Chen,K. Lear, and A.M.Raza, "Design of CMOS Transimpedance Amplifier for On-Chip Waveguide Based Optical Clock Distribution System," Proc. of SPIE Conference on Microtechnologies for the New Millenium, Gran Canaria, Spain, May 2-4, 2007. | 2007 |
| Non-Refereed Journal Articles / Chapters / Proceedings / Transactions | Top | |
| 103 | C. Jena, T. Mason, and Tom Chen, “On Power & Performance Tradeoff of L2 Cache Compression”, 2010 IEEE APCCAS. Kuala Lumpur, Malaysia, Dec. 6–9, 2010. | 2010 |
| 102 | Z. Cashero, A. Chen, R. Hoppal, T. Chen, “Fast Evaluation of Analog Circuits Using Linear Programming”, 2010 IEEE Computer Society Annual Symposium on VLSI, Lixouri, Kefalonia, Greece, July 5–7, 2010. | 2010 |
| 101 | A. Chen, R. Hoppal, and T. Chen, “On CMOS Memory Design In Low Supply Voltage For Integrated Biosensor Applications”, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Lille, France, Sept. 1–3, 2010 | 2010 |
| 100 | T.Wu, C. Alkan, and T. Chen, Complexity Reduction for Analog Circuit Performance Models Using Random Forests", 17th IFIP/IEEE Int. Conf. on VLSI, Florianopolis, Brazil, Oct. 12 { 14, 2009. | 2009 |
| 99 | T. Wu, C. Alkan, and T. Chen, Analysis and Improvement of SER Immunity of Combinational Logic", 16th IFIP/IEEE Int. Conf. on VLSI (VLSI-SOC 2008), Rhodes Island, Greece, Oct. 13 { 15, 2008. | 2008 |
| 98 | V. Nawale, T. Chen, "Optimal Useful Clock Skew Scheduling In the Presence of Variations Using Robust ILP-Formulations", Int. Conf. on Computer-Aided Design (ICCAD), November, 2006. | 2006 |
| 97 | R. Pownall, G. Yuan, T. Chen, P. Nikkel, and K.L. Lear, "Geometry Dependence of Leaky-Mode Waveguide-Coupled Polysilicon Photodetector", LEOS, November, 2006 | 2006 |
| 96 | J. Sridharan and T. Chen, "Modeling Multiple Input Switching of CMOS Gates in DSM Technology using HDMR", Design and Test in Europe (DATE2006), Munich, Germany, March 6-10, 2006. | 2006 |
| 95 | C. Alkan and T. Chen, "Routing-Tree Construction with Concurrent Performance, Power and Congestion Optimization", 2006 IEEE Computer Society Annual Symposium on VLSI, Karlsruhe, Germany, March 2-3, 2006. | 2006 |
| 94 | J. Sridharan and T. Chen, "Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis", 19th International Conference on VLSI Design, Hyderabad, India, January 3 - 7, 2006. | 2006 |
| 93 | C. Alkan and T. Chen, "A Progressive Two-Stage Global Routing for Macro-Cell based Designs", 19th International Conference on VLSI Design, Hyderabad, India, January 3-7, 2006. | 2006 |
| 92 | Justin Gregg, Tom Chen, and Katherine McDonnell, "Work in Progress: PEER College Summer Camp", Frontier in Education Conference, Oct. 19-22, Indianapolis, 2005. | 2006 |
| 91 | Justin Gregg and Tom Chen, PEER: Enriching Secondary Engineering Education Through a College Summer Camp", 2005 International Conference on Microelectronic Systems Education, Anaheim, CA, June 12-13, 2005. | 2005 |
| 90 | Vinil Varghese, Tom Chen, Peter Young, "On Stability of Active Clock Deskewing Systems Using a Control Theoretic Approach," 2005 American Control Conference (ACC2005), Portland, OR, June 8-10, 2005. | 2005 |
| 89 | D. M. Sendek, D. Balhiser, J. Gregg, and T. Chen, "Post Silicon Power-Performance Optimization in VLSI Design", Proceedings of 2005 SIAM Conference on Optimization, Stockholm, Sweden, May 16-19, 2005. | 2005 |
| 88 | C.V. Thangaraj, K. Stephenson, T. Chen, K. Lear, and A.M. Raza, "Design of CMOS Transimpedance Amplifier for On-Chip Waveguide Based Optical Clock Distribution System", Proc. of SPIE Conference on Mirotechnologies for the New Millennium, Sevilla, Spain, May 9-11, 2005. | 2005 |
| 87 | J. Gregg and T. Chen, "Optimization of Individual Well Adaptive Body Biasing (IWABB) Using a Multiple Objective Evolutionary Algorithm," International Symposium on Quality Electronic Design, San Jose, CA, March 21-23, 2005. | 2005 |
| 86 | V. Varghese, T. Chen and P. Young, "Systematic Analysis of Active Clock Deskewing Systems Using Control Theory", Design and Test in Europe (DATE2005), Munich, Germany, March 7-11, 2005. | 2005 |
| 85 | A. Chandy and T. Chen, "Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions," Design and Test in Europe (DATE2005), Mu- nich, Germany, March 7-11, 2005. | 2005 |
| 84 | J. Pratt, M. Aydin, T. Chen, "RC Extraction of Interconnects at Sub-Wavelength Dimensions," IASTED International Conference on Artificial Intelligence and Applications, Innsbruck, Austria, February 14-16, 2005. | 2005 |
| 83 | V. Varghese, T. Chen and P. Young, "Stability Analysis of Active Clock Deskewing Systems Using a Control Theoretic Approach," 2005 Asia and South Pacific Design Automation Conference (ASP-DAC), Shanghai, China, January 18-21, 2005. | 2005 |
| 82 | A.M. Raza, G.W. Yuan, K.L. Lear, T. Chen, and C.K. Thangaraj, "Truly CMOS Compatible Waveguide Coupled Photodiode for On-Chip Optical Interconnects," Conference on CMOS Compatible Photodetectors, IEEE LEOS, Puerto Rico, November 7-11, 2004. | 2004 |
| 81 | A.M. Raza, G.W. Yuan, K.L. Lear, T. Chen, and C.K. Thangaraj, "Waveguide Coupled CMOS Photodetector for On-Chip Optical Interconnects," Conf. on Photonic Devices and Algorithms for Computing, Proc. of SPIE, SPIE Annual Meeting. Denver, CO. August 2-6, 2004. | 2004 |
| 80 | A.M. Raza, G.W. Yuan, K.L. Lear, T. A. Andrew, A. O'Fallon, and T. Chen, "RUBASTEM: A Veri¯cation Method for Testing VHDL Behavioral Models," 8th IEEE International Symposium on High Assurance Systems Engineering (HASE), Tempa, FL, March 25-26, 2004. | 2004 |
| 79 | T. Chen and J. Gregg, "A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement In the Presence of Intra-Die Variations," Design and Test in Europe (DATE2004), Paris, France, February 2004. | 2004 |
| 78 | J. Gregg and T. Chen, "Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well Adaptive Body Biasing (IWABB)," 5th International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2004. (Nominated for best paper) | 2004 |
| 77 | M. Kulkami and T. Chen, "A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects," 5th International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2004. (Nominated for best paper) | 2004 |
| 76 | G. Esch and T. Chen, "Design of CMOS Drivers with Less Sensitivity to Process, Voltage, and Temperature Variations," 2nd IEEE Workshop on Electronic Design, Test and Applications (DELTA 2004), Perth, Australia, January 26-28, 2004. | 2004 |
| 75 | A. Andrew, A. O'Fallon, and T. Chen, "A Rule-Based Software Testing Method for VHDL Programs," IFIP 2003 VLSI System-on-Chip (SoC) Conference, Darmstadt, Germany, December 1-3, 2003. | 2003 |
| 74 | T. Chen and A. Hajjar, "Analyzing Static Timing Behavior of Coupled Intercon- nects Using Quadratic Delay Change Characteristics," 4th International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 24-26, 2003. | 2003 |
| 73 | G. Cho and T. Chen, "Comparative Assessment of Adaptive Body-Bias SOI Pass- Transistor Logic," 4th International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 24-26, 2003. | 2003 |
| 72 | C. Deshpande and T. Chen, "Design of 0.18um CMOS Test Chip for Power Grid and I/O Characteristics Verification," 2003 Asia and South Pacific Design Automation Conference (ASP-DAC), January 22-24, 2003. | 2003 |
| 71 | G. Cho and T. Chen, "On Single/Dual-Rail Mixed PTL/Static Circuits in Floating Body SOI and Bulk CMOS: A Comparative Assessment," 16th International Confer- ence on VLSI Design. New Delhi, India, January 4-8, 2003. | 2003 |
| 70 | G. Cho and T. Chen, "Application of Genetic Learning to Pass-Transistor Design and Optimization," 4th Asia-Pacific Conference on Simulated Evolution and Learning, Singapore, November 18-22, 2002. | 2002 |
| 69 | G. Cho and T. Chen, "On the Impact of Technology Scaling On Mixed PTL/Static Circuits," IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD), Freiburg, Germany, September, 16-18, 2002. | 2002 |
| 68 | G. Cho and T. Chen, "On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis in UDSM CMOS Process," IEEE/ACM 11th International Workshop on Logic and Synthesis, New Orleans, Louisiana, June 4-7, 2002. | 2002 |
| 67 | G. Cho and T. Chen, "Technology Mapping for Low Power SOC Using Genetic Algorithm," IFIP International Conference on Very Large Scale Integration, Montpellier, France, December 3-5, 2001. | 2001 |
| 66 | J. Kim and T. Chen, "Real-time Video Objects Segmentation using a Highly Pipelined Microarchitecture," International Conference Visualization, Imaging, and Image Processing (VIIP2001), Marbella, Spain, September 3-5, 2001 | 2001 |
| 65 | T. Chen, "On the Impact of On-Chip Inductance on Signal Nets Under the Influence of Power Grid Noise," Design Automation and Test in Europe (DATE2001), Munich, Germany, March, 2001. | 2001 |
| 64 | A. Hajjar, T. Chen, I. Munn, A. von Mayrhauser, and M Bjorkman, "High Quality Behavioral Verification Using Statistical Criteria," Design Automation and Test in Europe (DATE2001), Munich, Germany, March, 2001. | 2001 |
| 63 | T. Chen, "On the Impact of On-Chip Inductance When Transitioning From Al to Cu Based Technology," International Symposium on Quality Electronic Design (ISQED). San Jose, CA, March, 2001. | 2001 |
| 62 | A. Hajjar, T. Chen, I. Munn, A. von Mayrhauser, and M Bjorkman, "High Quality Behavioral Verification Using Statistical Criteria," Design Automation and Test in Europe (DATE2001), Munich, Germany, March, 2001. | 2001 |
| 61 | T. Chen, "On the Impact of On-Chip Inductance When Transitioning From Al to Cu Based Technology," International Symposium on Quality Electronic Design (ISQED). San Jose, CA, March, 2001. | 2001 |
| 60 | A. Hajjar, T. Chen, I. Munn, A. von Mayrhauser, and M. Bjorkman, "Stopping Criteria Comparison: Towards High Quality Behavioral Verification," International Symposium on Quality Electronic Design (ISQED). San Jose, CA, March, 2001. | 2001 |
| 59 | J. Kim and T. Chen, "Low-Complexity Fusion of Intensity, Motion, Texture and Edge for Image Sequence Segmentation: A Neural Network Approach," IEEE International Workshop on Neural Networks for Signal Processing, Sydney, Australia, December 2000. | 2000 |
| 58 | A. von Mayrhauser, T. Chen, J. Kok, C. Anderson, A. Reed, and A. Hajjar, "On Choosing Test Criteria for Behavioral Design Verification," IEEE International High Level Validation and Test Workshop, Berkeley, CA, November 2000. | 2000 |
| 57 | A. Hajjar, T. Chen, and A. von Mayrhauser, "On Statiscal Behavior of Branch Coverage in Testing Behavioral VHDL Models," IEEE International High Level Design Validation and Test Workshop, Berkeley, CA, November 2000. | 2000 |
| 56 | J. Kim and T. Chen, "A VLSI Architecture for Image Sequence Segmentation Us- ing Edge Fusion," International Workshop on Computer Architectures for Machine Perception, Padova, Italy, September 2000. | 2000 |
| 55 | J. Kim and T. Chen, "Segmentation of Image Sequences Using SOFM Networks," 15th International Conference on Pattern Recognition, Barcelona, Spain, September 2000. | 2000 |
| 54 | J. Kim and T. Chen, "Neural Network Based Image Sequence Segmentation Using Multiple Features and Edge Fusion," Advanced Concepts for Intelligent Vision Systems Symposium, Baden-Baden, Germany, July 2000. | 2000 |
| 53 | J. Kim and T. Chen, "An Integrated Approach to Image Sequence Segmentation," IEEE Nordic Signal Processing Symposium, Vildmarkshotellet, Sweden, June 2000. | 2000 |
| 52 | T. Chen, M. Sahinoglu, A. von Mayrhauser, A. Hajjar, and C. Anderson, "Achieving the Quality of Verification for Behavioral Models with Minimum Effort," IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 20-22, 2000. | 2000 |
| 51 | T. Chen and C. Alkan, "Measuring Routing Congestion for Multi-layer Global Rout- ing," 10th Great Lakes Symposium on VLSI, Chicago, Illinois, March 2-4, 2000. | 2000 |
| 50 | T. Chen, I. Munn, A. von Mayrhauser, A. Hajjar, "Efficient Verification of Behavioral Models Using the Sequential Sampling Technique," 10th IFIP International Conference on VLSI (VLSI99), Lisboa, Portugal, December 1-4, 1999. | 1999 |
| 49 | T. Chen, M. Sahinoglu, A. von Mayrhauser, A. Hajjar, and C. Anderson, "How Much Testing is Enough? Applying Stopping Rules to Behavioral Model Testing," 4th IEEE International Symposium on High Assurance System Engineering, Washington D.C., November, 17-19, 1999. | 1999 |
| 48 | . Kim and T. Chen, "Integration of Multiple Features Using Back Propagation Neural Networks for Segmentation of Image Sequences," International Conference on Image Science, Systems, and Technology, pp.65-71, Las Vegas, NV, June, 1999. | 1999 |
| 47 | M. Sahinoglu, A. von Mayrhauser, A. Hajjar, T. Chen, and C. Anderson, "On the Efficiency of a Compound Poisson Stopping Rule for Mixed Strategy Testing", Proc. 1999 IEEE Aerospace Conference, Snowmass, Colorado, March 6-13, 1999. | 1999 |
| 46 | T. Chen, D. Anderson, P. Young "On Integrating Multi-Sensory Components In Virtual Environments," 4th International Conference on Virtual Systems and MultiMedia, Gifu, Japan, November 18-20, 1998. | 1998 |
| 45 | A. von Mayrhauser, A. Bai, T. Chen, A. Hajjar, C. Anderson, "Fast Antirandom (FAR) Test Generation," 3rd IEEE High-Assurance Systems Engineering Symposium, Washington, DC. November 13-14, 1998. | 1998 |
| 44 | A. Bai, T. Chen, A. von Mayrhauser, A. Hajjar, C. Anderson, "Fast Antirandom (FAR) Test Generation to Improve Code Coverage," Quality Week '98, San Francisco, CA, May 27-30, 1998. | 1998 |
| 43 | T. Chen, P. Young, D. Anderson, "Development of a Stereoscopic Haptic Acoustic Real-Time Computer(SHARC)," Proceedings of SPIE, Vol. 3295, pp. 171-179, San Jose, CA, January 26-29 1998. | 1998 |
| 42 | P. Young, T. Chen, D. Anderson, "Legoworld: A Multisensory Environment for Virtual Prototyping," Proceedings of SPIE, Vol. 3295, pp. 313{321, San Jose, CA, 26-29 January 1998. | 1998 |
| 41 | T. Chen, P. Young, D. Anderson, "Creating Virtual Environments Over the Internet," Proceedings of SPIE, Vol. 3295, pp. 322-331, San Jose, CA, 26-29 Jan. 1998. | 1998 |
| 40 | V.Y. Kim, T. Chen, and M. Tegethoff, "ASIC Manufacturing Test Cost Prediction at Early Design Stage," 1997 International Test Conference, Washington D.C. November 3-5, 1997. | 1997 |
| 39 | C. Chen and T. Chen, "Modified Rate-Distortion Function With Optimal Classiffication for Wavelet Coding," 1997 International Conference on Image Processing, Santa Barbara, CA, October 26-29, 1997. | 1997 |
| 38 | A. Hajjar and T. Chen, "A New Real-Time Edge Linking Algorithm and Its VLSI Implementation," International Conference on Computer Architectures for Machine Perception (CAMP'97), Boston, MA, October 20-22, 1997. | 1997 |
| 37 | V.Y. Kim and T. Chen, "IDDQ Testability Analysis Using Random Test Vectors," 5th International Conference on VLSI and CAD, Seoul, Korea, October 13-15, 1997. | 1997 |
| 36 | C. Chen, J. Swanson, and T. Chen, "Applying High-Order Polynomial Type Global Constraints to Stereo Image Coding," 1997 Picture Coding Symposium, Berlin, Germany, September 10-12, 1997. | 1997 |
| 35 | C. Chen and T. Chen, "Wavelet Coding By Using Interpolated Rate-Distortion Function and Classified VQ," 1997 Picture Coding Symposium, Berlin, Germany, September 10-12, 1997. | 1997 |
| 34 | C. Chen, J. Swanson, and T. Chen, "Stereo Image Coding Using Object-Based Global Constraints," International Workshop on Synthetic-Natural Hybrid Coding and Three Dimensional imaging, Rhodes, Greece, September 5-9, 1997. | 1997 |
| 33 | A. Hajjar and T. Chen, "A VLSI Architecture for Real-Time Edge Linking," IX IFIP International Conference on VLSI, Gramado, Brazil, August 26-29, 1997. | 1997 |
| 32 | V.Y. Kim and T. Chen, "SRAM Yield Estimation in the Early Stage of the Design Cycle," 1997 IEEE International Workshop on Memory Technology, Design and Testing, San Jose, CA, August 11-12, 1997. | 1997 |
| 31 | C. Anderson, A. von Mayrhauser, C.R. Gideon, T. Chen, and J. Kok, "Test Coverag Prediction of VHDL Models Using Neural Networks," Annual Oregon Workshop on Software Metrics, May 11-13, 1997. | 1997 |
| 30 | V.Y. Kim and T. Chen, "Assessing SRAM Test Coverage for Sub-Micron CMOS Technologies," 1997 VLSI Test Symposium, Monterey, CA, April 27-30, 1997. | 1997 |
| 29 | F. Alzahrani and T. Chen, "A Real-Time High Performance Edge Detector for Vision Applications," 1997 Asia and South Pacific Design Automation Conference, (ASP-DAC'97) Makurahi Messe, Chiba, Japan, January 28-31, 1997. | 1997 |
| 28 | Y.B. Kim and T. Chen, "A CMOS Delayed Locked Loop (DLL) for Reducing Clock Skew to under 500ps," 1997 Asia and South Pacific Design Automation Conference, (ASP-DAC'97) Makurahi Messe, Chiba, Japan, January 28-31, 1997. | 1997 |
| 27 | C. Chen and T. Chen, "Hybrid Optimum Classiffication in Wavelet Transform Coding," 1996 International Symposium on Multi-Technology Information Processing, Hsinchu, Taiwan, December 16-18, 1996. | 1996 |
| 26 | F. Alzahrani and T. Chen, "A Stand-Alone ASIC for Real-Time Edge-Detection," 8th International Conference on Microelectronics, Egypt, December 16{18, 1996. | 1996 |
| 25 | Y.B. Kim and T. Chen, "A 0.8 mu-m CMOS Delayed Loop for VLSI Systems with Sub-50ps Clock Skew," 1996 IEEE Asia-Pacific Conference on Circuits and Systems, (APCCAS'96) Seoul, Korea, November 18-21, 1996. | 1996 |
| 24 | C. Chen and T. Chen, "Wavelet Coding With Region Classification Using Low-Complexity Prediction Model," 13th Asilomar Conference on Signals, Systems, and Computers, Monterey, CA, November 3-6, 1996. | 1996 |
| 23 | V.Y. Kim, M. Tegethoff, and T. Chen, "Yield Estimation of ASIC Chips at Early Stage of the Design Cycle," 1996 International Test Conference, Washington D.C., November 1996. | 1996 |
| 22 | Y.B. Kim and T. Chen, "On System Level Performance of DRAM/Logic Merged Technology," 1996 International Conference on Circuits/Systems, Computers and Communications, Seoul, Korea, July 15-17, 1996. | 1996 |
| 21 | Y.B. Kim and T. Chen, "Clock Skew on DRAM/Logic Merged Technology Based Systems," 1996 International Symposium on Circuits and Systems (ISCAS), Atlanta, GA, May 12-15, 1996. | 1996 |
| 20 | Y.B. Kim and T. Chen, "On System Level Performance of DRAM/Logic Merged Technology," 1996 International Conference on Circuits/Systems, Computers and Communications, Seoul, Korea, July 15-17, 1996. | 1996 |
| 19 | Y.B. Kim and T. Chen, "Assessing DRAM/Logic Merged Technology," 1996 International Symposium on Circuits and Systems (ISCAS), Atlanta, GA, May 12-15, 1996. | 1996 |
| 18 | C. Anderson, A. von Mayrhauser, and T. Chen, "Assessing Neural Networks as Guides for Testing Activities," 3rd International Software Metrics Symposium, Berlin, Germany, March 1996. | 1996 |
| 17 | Y.B. Kim, V.Y. Kim, and T. Chen, "A 0.8 mu-m CMOS Optical Clock Receiver Design," The 7th International Conference on Microelectronics, Kuala Lumpur, Malaysia, December 18-21, 1995. | 1995 |
| 16 | M. Schaffer and T. Chen, "A VLSI Architecture for 2D Object Classi¯cation Based on Tree Matching ," Computer Architectures for Machine Perception (CAMP95), Como, Italy, September 18-20, 1995. | 1995 |
| 15 | M. Schaffer and T. Chen, "Object Parts Matching Using Hopfield Neural Networks," Computer Architectures for Machine Perception (CAMP95), Como, Italy, September 18-20, 1995. | 1995 |
| 14 | C. Morganti and T. Chen, "Graceful Capacity Degradation for Ultra-Large Hierarchical Memory Structures," 1995 IFIP VLSI Conference, Chiba, Japan, August 30 - September 1, 1995. | 1995 |
| 13 | M. Tegethoff and T. Chen, "Manufacturing Test Simulator: A Concurrent Engineering Tool for Boards and MCMs," 1994 International Test Conference, Washington D.C., October 1994. | 1994 |
| 12 | M. Tegethoff and T. Chen, "Board Test: Defects, Fault Coverage, Yield and Cost in Board Manufacturing," 1994 International Test Conference, Washington D.C., October 1994. | 1994 |
| 11 | F. Alzahrani and T. Chen, "On-Chip TEC-QED ECC for Ultra-Large, Single-Chip Memory Systems," 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD), Cambridge, MA, October, 1994. | 1994 |
| 10 | G. Sunada, J. Jin, M. Berzins, and T. Chen, "COBRA: A 1.2 Million Transistor Expandable Column FFT Chip," 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD), Cambridge, MA, October, 1994. | 1994 |
| 9 | M. Tegethoff and T. Chen, "On Clustering of Defects and Yield of SMT Assemblies," 1994 IEEE International Conference on Manufacturing Engineering, San Diego, CA, September 1994. | 1994 |
| 8 | G. Sunada and T. Chen, "A Novel DCT Implementation Using Bit-Serial Arithmetic," 1994 IEEE Data Compression Conference, Snowbird, Utah, March, 1994. | 1994 |
| 7 | T. Chen and G. Sunada, "SIMSTGEN: A Simulation Based ATPG For Synchronous Sequential Circuits," Annual Symposium of Technology Transfer Program, Colorado Advanced Software Institute, Denver, CO. 1992. | 1992 |
| 6 | T. Chen and G. Sunada, "An Ultra-Large Capacity Single-Chip Memory Architecture With Self-Testing and Self-Repairing," IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD), Boston MA, October 1992. (Recommended for Best Paper Award) | 1992 |
| 5 | T. Chen, D. Louderback, and G. Sunada, "Optimization of the Number of Levels of Hierarchy in Large-Scale Hierarchical Memory Systems," International Symposium on Circuits and Systems (ISCAS). San Diego, CA, 1992. | 1992 |
| 4 | T. Chen and G. Sunada, "A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity Memories," 1992 International Test Conference, Baltimore, MD, September 20-24, 1992. | 1992 |
| 3 | T. Chen and L. Zhu, "A Fast 1024-Point FFT Architecture", 1991 International Conference on Parallel Processing, St. Charles, Illinois, 1991. | 1991 |
| 2 | T. Chen, J. Mavor, P.B. Denyer, D. Renshaw, "A ULSI Architecture for Reconfigurable Serial Systems," 13th European Solid-State Circuits Conference, Bad Soden, Germany. September 23-25, 1987. | 1987 |
| 1 | T. Chen, P.B. Denyer, J. Mavor, D. Renshaw, "Fault-tolerantWafer Scale Architectures Using Large Crossbar Switches," International Workshop on Wafer Scale Integration, North Holland, 1986. | 1986 |