Dr. Sudeep Pasricha

Publications

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  books Top
1 S. Pasricha and N. Dutt, "On-Chip Communication Architectures", Morgan Kauffman, ISBN 978-0-12-373892-9, Apr 2008 2008
 
  Refereed Journal Articles Top
19 1. Y. Park, S. Pasricha, F. Kurdahi, N. Dutt, “A Multi-Granularity Power Modeling Methodology for Embedded Processors”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 19, No. 4, pp. 668-681, Apr 2011. 2011
18 2. D. Young, J. Apodaca, L. Briceno, J. Smith, S. Pasricha, A. Maciejewski, H. Siegel, S. Bahirat, B. Khemka, A. Ramirez and Y. Zou, “Deadline and Energy Constrained Dynamic Resource Allocation in a Heterogeneous Computing Environment”, accepted for publication, Journal of Supercomputing, 2012. 2011
17 3. N. Kapadia, S. Pasricha, “A Framework for Low Power Synthesis of Interconnection Networks-on-Chip with Multiple Voltage Islands”, accepted for publication, Integration, the VLSI Journal, 2012. 2011
16 4. L. Bathen, Y. Ahn, S. Pasricha, N. Dutt, “MultiMaKe: Chip-Multiprocessor Driven Memory-aware Kernel Pipelining”, accepted for publication, IEEE Transactions on Embedded Computing Systems (TECS), 2012. 2011
15 Y. Zou, S. Pasricha, "NARCO: Neighbor Aware Turn Model Based Fault Tolerant Routing for NoCs", IEEE Embedded System Letters, Vol. 2, No. 3, Sep 2010 2010
14 S. Pasricha, F. Kurdahi, N. Dutt, "Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 18, No. 9, pp. 1376-1380, Sep 2010 2010
13 S. Pasricha, Y. Park, F. Kurdahi, N. Dutt, "CAPPS: A Framework for Power-Performance Trade-Offs in Bus Matrix Based On-Chip Communication Architecture Synthesis", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 18, No. 2, pp. 209-221, Feb 2010 2010
12 G. Madl, S. Pasricha, N. Dutt, S. Abdelwahed, "Cross-abstraction Functional Verification and Performance Analysis of Chip Multiprocessor Designs", IEEE Transactions on Industrial Informatics (TII), Vol. 5, No. 3, Aug 2009 2009
11 D. Cho, S. Pasricha, I. Issenin, N. Dutt, Y. Paek , "Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (TCAD), Vol. 28, No. 4, pp. 554-567, Apr 2009 2009
10 S. Pasricha, Y. Park, F. Kurdahi, N. Dutt, "System-level PVT Variation Aware Power Exploration of On-Chip Communication Architectures", ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 14, No. 2, pp. 20:1-20:25, Mar 2009 2009
9 S. Pasricha, N. Dutt, "Trends in Emerging On-Chip Interconnect Technologies", IPSJ Transactions on System LSI Design Methodology, Vol. 1, Sep 2008 2008
8 S. Pasricha, N. Dutt and M. Ben-Romdhane, "Fast Exploration of Bus-based Communication Architectures at the CCATB Abstraction", IEEE Transactions on Embedded Computing Systems (TECS), Feb 2008 2008
7 S. Pasricha, N. Dutt and M. Ben-Romdhane, "BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (TCAD), vol.26, no.8, pp.1454-1464, Aug 2007 2007
6 S. Pasricha and N. Dutt, "A Framework for Co-synthesis of Memory and Communication Architectures for MPSoC", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 3, pp. 408-420, Mar 2007 2007
5 C. Shin, P. Grun, N. Romdhane, C. Lennard, G. Madl, S. Pasricha, N. Dutt and M. Noll, "Enabling Heterogeneous Cycle-Based and Event-Driven Simulation in a SPIRIT-Enabled Design Flow", Kluwer Journal on Design Automation of Embedded Systems (DAES), Feb 2007 2007
4 S. Pasricha, N. Dutt, E. Bozorgzadeh and M. Ben-Romdhane, "FABSYN: Floorplan-aware Bus Architecture Synthesis", IEEE Transactions on Very Large Scale Integration Systems (TVLSI) Vol 14, No. 3, pp 241-253, Mar 2006 2006
3 S. Pasricha, N. Dutt, E. Bozorgzadeh and M. Ben-Romdhane, "FABSYN: Floorplan-aware Bus Architecture Synthesis", IEEE Transactions on Very Large Scale Integration Systems (TVLSI) Vol 14, No. 3, pp 241-253, Mar 2006 2006
2 S. Pasricha, M. Luthra, S. Mohapatra, N. Dutt, N. Subramanian, "Dynamic Backlight Adaptation for Low Power Handheld Devices", IEEE Design and Test (IEEE D&T), Special Issue on Embedded Systems for Real Time Embedded Systems, Sep-Oct 2004 2004
1 S. Pasricha, S. Mohapatra, M. Luthra, N. Dutt and N. Subramanian, "Co-optimization of Streaming Multimedia QoS and Backlight Power Consumption for Mobile Handheld Devices", Journal of Korean Multimedia Society (KSSM), Dec 2003 2003
 
  Refereed Conference Proceedings Top
22 L. A. D. Bathen, S. Pasricha, N. Dutt, "A Framework for Memory-aware Multimedia Application Mapping on Chip-Multiprocessors", IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia) Oct 2008 2008
21 Y. Park, S. Pasricha, F. Kurdahi, N. Dutt, "Methodology for Multi-Granularity Embedded Processor Power Model Generation for an ESL Design Flow", IEEE/ACM CODES+ISSS Oct 2008 2008
20 S. Pasricha, F. Kurdahi, N. Dutt, "System Level Performance Analysis of Carbon Nanotube Global Interconnects for Emerging Chip Multiprocessors", IEEE/ACM NanoArch Jun 2008 2008
19 H. Homayoun, S. Pasricha, M. Makhzan, A. Veidenbaum, "Dynamic Register File Resizing to Improve Embedded Processor Performance and Energy-delay Efficiency", IEEE/ACM DAC Jun 2008 2008
18 D. Cho, S. Pasricha, I. Issenin, N. Dutt and Y. Paek, "Compiler Driven Data Layout Optimization for Regular/Irregular Array Access Patterns", ACM LCTES Jun 2008 2008
17 H. Homayoun, S. Pasricha, M. Makhzan, A. Veidenbaum, "Improving Performance and Reducing Energy-Delay with Adaptive Resource Resizing for Out-of-Order Embedded Processors", ACM LCTES Jun 2008 2008
16 S. Pasricha, Y. Park, F. Kurdahi, N. Dutt, "Incorporating PVT Variations in System-level Power Exploration of On-Chip Communication Architectures", IEEE VLSI Design Conference (VLSID 2008), Bangalore, India, January 2008 2008
15 S. Pasricha, N. Dutt, "ORB: An On-chip Optical Ring Bus Communication Architecture for Multi-Processor Systems-on-Chip", IEEE Asia & South Pacific Design Automation Conference (ASPDAC 2008), Seoul, Korea, January 2008 2008
14 Y. Park, S. Pasricha, F. Kurdahi, N. Dutt, "System Level Power Estimation Methodology with H.264 Decoder Prediction IP Case Study", IEEE International Conference on Computer Design (ICCD 2007), Great Lakes, CA, Oct 2007 2007
13 S. Pasricha, N. Dutt, "On-chip Communication Architecture Synthesis for High Performance MPSoCs", SRC TechConnect, Nov 2007 2007
12 S. Pasricha, Y. Park, F. Kurdahi, N. Dutt, "System-Level Power-Performance Trade-Offs in Bus Matrix Communication Architecture Synthesis", IEEE/ACM International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS 2006), Seoul, Korea, October 2006 2006
11 G. Madl, S. Pasricha, Q. Zhu, L. Bathen and N. Dutt, "Formal Performance Evaluation of AMBA-based System-on-Chip Designs", 6th Annual ACM Conference on Embedded Software (EMSOFT 2006), Seoul, Korea, October 2006 2006
10 S. Pasricha and N. Dutt, "COSMECA: Application Specific Co-Synthesis of Memory and Communication Architectures for MPSoC", IEEE Design Automation and Test in Europe Conference (DATE 2006), Munich, Germany, March 2006 2006
9 S. Pasricha, N. Dutt and M. Ben-Romdhane, "Constraint-Driven Bus Matrix Synthesis for MPSoC", IEEE Asia & South Pacific Design Automation Conference (ASPDAC 2006), Yokohama, Japan, January 2006 (Best Paper Award) 2006
8 S. Pasricha, N. Dutt and M. Ben-Romdhane, "Using TLM for Exploring Bus-based SoC Communication Architectures", IEEE Conference on Application-specific Systems, Architectures and Processors (ASAP 2005), Samos, Greece, July 2005 2005
7 S. Pasricha, N. Dutt, E. Bozorgzadeh and M. Ben-Romdhane, "Floorplan-aware Automated Synthesis of Bus-based Communication Architectures", IEEE Design Automation Conference (DAC 2005), Anaheim, CA, June 2005 (Best Paper Award Candidate) 2005
6 S. Pasricha, N. Dutt and M. Ben-Romdhane, "Automated Throughput-driven Synthesis of Bus-based Communication Architectures", IEEE Asia South Pacific Design Automation Conference (ASPDAC 2005), Shanghai, China, January 2005 2005
5 S. Pasricha, N. Dutt, M. Ben-Romdhane, "Fast Exploration of Bus-based On-chip Communication Architectures", IEEE International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS 2004), Stockholm, Sweden, September 2004 2004
4 S. Pasricha, N. Dutt and M. Ben-Romdhane, "Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration", IEEE Design Automation Conference (DAC 2004), San Diego, CA, June 2004 2004
3 S. Pasricha, S. Mohapatra, M. Luthra, N. Dutt and N. Subramanian, "Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices", IEEE Embedded Systems for Real-Time Multimedia (ESTIMEDIA 2003), Newport Beach, CA, October 2003 2003
2 S. Pasricha and A. Veidenbaum, "Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches" IEEE International Conference on Computer Design (ICCD 2003), San Jose, CA, October 2003 2003
1 S. Pasricha, "Transaction Level Modeling of SoC using SystemC 2.0" Synopsys User Group Conference (SNUG 2002), Bangalore, May 2002 2002
 
  Non-Refereed Journal Articles / Chapters / Proceedings / Transactions Top
16 S. Pasricha and N. Dutt, “On-chip optical ring bus communication architecture for heterogeneous MPSoC”, Integrated Optical Interconnect Architectures and Applications in Embedded Systems”, Springer Press 2011
15 S. Kwon, S. Pasricha, "POSEIDON: A Framework for Application-Specific Network-on-Chip Synthesis for Heterogeneous Chip Multiprocessors", IEEE ISQED, 2011 2011
14 S. Pasricha, Y. Zou, "A Low Overhead Fault Tolerant Routing Scheme for 3D Networks-on-Chip", IEEE ISQED, 2011 2011
13 S. Pasricha, Y. Zou, " NS-FTR: A Fault Tolerant Routing Scheme for Networks on Chip with Permanent and Runtime Intermittent Faults", IEEE/ACM ASPDAC 2011 2011
12 S. Pasricha, S. Bahirat, " OPAL: A Multi-Layer Hybrid Photonic NoC for 3D ICs", IEEE/ACM ASPDAC 2011 2011
11 S. Pasricha, Y. Zou, D. Connors, H. J. Seigel, "OE+IOE: A Novel Turn Model Based Fault Tolerant Routing Scheme for Networks-on-Chip", IEEE/ACM CODES+ISSS, Oct 2010 2010
10 S. Pasricha, "Carbon Nanotube Global Interconnects for Emerging Chip Multiprocessors", 21st Annual Workshop on Interconnections within High Speed Digital Systems (HSD), May 2010 2010
9 S. Bahirat, S. Pasricha, "UC-PHOTON: A Novel Hybrid Photonic Network-on-Chip for Multiple Use-Case Applications", IEEE ISQED Mar 2010 2010
8 L. A. D. Bathen, Y. Ahn, S. Pasricha, N. Dutt, "A Methodology for Power-aware Pipelining via High-Level Performance Model Evaluations", IEEE International Workshop on Microprocessor Test and Verification (MTV), Dec 2009 2009
7 L. A. D. Bathen, Y. Ahn, N. Dutt, S. Pasricha, "Inter-kernel Data Reuse and Pipelining on Chip-Multiprocessors for Multimedia Applications", IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia) Oct 2009 2009
6 S. Bahirat, S. Pasricha, "Exploring Hybrid Photonic Networks-on-Chip for Emerging Chip Multiprocessors", IEEE/ACM CODES+ISSS Oct 2009 2009
5 S. Pasricha, "Exploring Serial Vertical Interconnects for 3D ICs", IEEE/ACM Design Automation Conference (DAC), Jul 2009 2009
4 R. Kost, D. Connors, S. Pasricha, "Characterizing the Use of Program Vulnerability Factors for Studying Transient Fault Tolerance in Multi-core Architectures", Workshop on Compiler and Architectural Techniques for Application Reliability and Security (CATARS) Jun 2009 2009
3 A. Gupta, S. Pasricha, N. Dutt, F. Kurdahi, K. Khouri, M. Abadir, "On-Chip Communication Architecture Based Thermal Management for SoCs", IEEE VLSI-DAT, Apr 2009 2009
2 S. Pasricha, N. Dutt, F. Kurdahi, "Dynamically Reconfigurable On-Chip Communication Architectures for Multi Use-Case Chip Multiprocessor Applications", IEEE Asia & South Pacific Design Automation Conference (ASPDAC), Jan 2009 2009
1 S. Pasricha, F. Kurdahi, N. Dutt, "Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications", IEEE VLSI Design Conference (VLSID), January 2009 2009
 
  Other (e.g.: Lab Texts, Book Reviews, Technical Reports, In-House Reports) Top
4 S. Pasricha, N. Dutt, L. Benini, “On-Chip Communication Architectures: Buses, Networks-on-Chip, and Beyond ”, Full day tutorial at 41st IEEE/ACM International Symposium on Microarchitecture (MICRO 2008), Lake Como, Italy, Nov 2008 2008
3 S. Pasricha, K. Lahiri, and N. Dutt, “Modeling, Analysis and Design of Bus-based SOC Communication Architectures”, Half day tutorial presented at IEEE Design Automation and Test in Europe Conference, (DATE 2007), Nice, France, April 2007 2007
2 S. Pasricha, K. Banerjee, L. Benini, K. Lahiri and N. Dutt, “SoC Communication Architectures: Technology, Current Practice, Research and Trends”, Full day tutorial presented at IEEE VLSI Design Conference (VLSID 2007), Bangalore, India, January 2007 2007
1 S. Pasricha and N. Dutt, "SoC Communication Architectures: Current Practice, Research and Trends", Half day tutorial presented at IEEE Asia and South Pacific Design Automation Conference (ASPDAC 2006), Yokohama, Japan, January 2006. 2006
 

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