ECE Seminar Series

ECE Department

Title: Circuit Locking: In Theory and in Practice
Speaker: Kaveh Shamsi
Affiliation: University of Florida
Day: Monday, March 23, 2020
Time: 11:00 am - 12:00 pm
Location: Video Conference

Abstract: The high costs of maintaining cutting-edge Integrated Circuit (IC) fabrication facilities has resulted in a consolidation of these fabs. A new paradigm has emerged in which designers from various sectors submit their chip designs for fabrication to large foundries that may be untrusted. In addition to the foundry, end-users can reverse engineer deeply scaled fabricated ICs through ever advancing microscopy techniques. This threatens the expensive intellectual property inherent to novel designs, plus raises the more serious concern of targeted malicious modification of the IC design by a foundry that has some understanding of how the chip operates. An array of design-time techniques were proposed a decade ago to "obfuscate" the IC design before it is sent to the foundry to help thwart some of these threats. This talk presents the state-of-art in our understanding of the security of these techniques against an array of advanced algorithmic attacks. It just so happens that studying/performing obfuscation and "de"-obfuscation of circuits requires using concepts and techniques from various disciplines: computational learning theory, formal-methods, automated theorem proving, discrete optimization, EDA algorithms, and cryptography, all of which are touched upon in this talk.

Bio: Kaveh Shamsi is a Ph.D. candidate at the ECE department at the University of Florida. He received a Bachelor's degree in Electrical Engineering from the Sharif University of Technology in Iran, and a Master's degree in Computer Engineering from the University of Central Florida. He has been an active researcher in the area of circuit obfuscation and hardware-oriented security for 6 years, receiving the best-paper-award from the Hardware Oriented Security and Trust (HOST) symposium in 2017, a best-paper-award from the Great-Lakes-Symposium on VLSI (GLSVLSI) in 2018, and a best-paper-candidate at the Design-and-Test in Europe Symposium (DATE) in 2019.