Give

Graduate Exam Abstract


Swapnil Bhosale

M.S. Final
October 19, 2018, 9:00 am - 11:00 am
ECE conference room
HIGH PERFORMANCE AND ENERGY EFFICIENT SHARED HYBRID LAST LEVEL CACHE ARCHITECTURE IN MULTICORE SYSTEMS

Abstract: As the performance gap between CPU
and main memory continues to
increase, it causes a
significant roadblock to exascale
computing. Memory performance has
not kept up with CPU
performance, and is becoming a
bottleneck today, particularly due to the
advent of data-intensive
applications. To accommodate the vast
amount of data required by these
applications, emerging
non-volatile memory technology
STTRAM (Spin-Transfer Torque
Random Access Memory) is
a good candidate to replace or
augment SRAM from last-level cache
(LLC) memory because of
its high capacity, good scalability, and
low power consumption. However, its
expensive write
operations prevent it from becoming a
universal memory candidate.
In this thesis, we propose an SRAM-
STTRAM hybrid last level cache (LLC)
architecture
that consumes less energy and
performs better than SRAM-only and
STTRAM-only LLC. We
design an algorithm to reduce write
operations to the STTRAM region of
the hybrid LLC and
consequently minimize the write
energy of STTRAM. Compared to two
prior state-of-the-art
techniques, our proposed technique
achieves 38.79% and 8.97% total LLC
energy savings and
6.863% and 0.407% performance
improvement for various SPLASH2
and PARSEC parallel
benchmarks.


Adviser: Dr. Sudeep Pasricha
Co-Adviser: N/A
Non-ECE Member: Dr. Wim Bohm
Member 3: Dr. Sourajeet Roy
Addional Members: N/A

Publications:
N/A


Program of Study:
ECE561
CS470
ECE554
ECE567
ECE569
ECE699
N/A
N/A