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- G. Yuan, R. Pownall, P. Nikkel, C. Thangaraj, T.W. Chen,
and K.L. Lear, \Characterization of CMOS compatible, waveguide
coupled leaky-mode photodetectors", IEEE
Photonics Technology Letters., vol. 18, pp. 1657-1659, August,
2006.
- M. Kulkarni and T. Chen, \A Sensitivity
Based Approach to Analyzing Signal Delay
Uncertainty of Coupled Interconects", IEEE Trans.
on Computer-Aided Design of
Integrated Circuits and Systems, Vol. 24, No. 9, pp. 1336{1346,
Sept. 2005. T. Chen, \On the Impact of On-Chip Inductance on
Signal Nets Under the In°uence of
Power Grid Noise," IEEE Trans. on VLSI Systems, Vol.13,
No.3, pp. 339{348, March,
2005.
- G. Cho and T. Chen, \Comparative Assessment of Adaptive
Body-Bias SOI Pass-Transistor Logic," An International
Journal of Analog Integrated Circuits and Signal
Processing, Kluwer Publications. Vol.42, pp. 219{229, March,
2005 T. Chen and A. Hajjar, \Statistical Timing Analysis
of Coupled Interconnects Using
Quadratic Delay Change Characteristics", IEEE Trans.
on Computer-Aided Design of
Integrated Circuits and Systems, Vol. 23, No. 12, pp. 1677{1683,
December 2004.
- G. Esch Jr. and T. Chen, \A Near Linear CMOS IO Driver
with Less Sensitivity to
Process, Voltage, and Temperature Variations," IEEE
Trans. on VLSI Systems. pp.
1253 { 1257, Vol. 12, No. 11, November 2004.
- G. Cho and
T. Chen, \Synthesis of Single/Dual-Rail Mixed PTL/Static
Logic for Low-
Power Applications," IEEE Trans. on Computer-Aided
Design of Integrated Circuits
and Systems, Vol. 22, No. 2, pp. 229{242, February 2004.G.
Cho and T. Chen, "Synthesis of Single/Dual-Rail
Mixed PTL/Static Logic for Low-Power Applications", accepted
for publication, IEEE Trans. on Computer-Aided Design
of Integrated Circuits and Systems, 2003.
- T. Chen and S. Narziger, "Comparison of
Adaptive Body Bias (ABB) And Adaptive Supply Voltage (ASV)
For Improving Delay and Leakage Under the Presence of Process
Variation", IEEE Trans. on VLSI Systems, Vol.11,
No.5, pp.888{899, Oct. 2003.
-
J. Kim and T. Chen, "Combining Static and
Dynamic Features Using Neural Networks and Edge Fusion
for Video Object Extraction", IEE Proceedings-Vision,
Image, and Signal Processing, Vol.150, No.3, pp.160{167,
June, 2003.
-
J. Kim and T. Chen, "A VLSI Architecture
for Video-Object Segmentation", IEEE Trans. on Circuits
and Systems for Video Technology (CSVT), Vol. 13,
No.1, pp.83{ 96, January, 2003
-
T. Chen, A. Bai, A. Hajjar, A. von Mayrhauser,
and C. Anderson, "Fast Antirandom (FAR) Test Generation
to Improve the Quality of Behavioral Model Verification",
Journal of Electronic Testing: Theory and Applications
(JETTA), Kluwer Academic Publishing, Vol. 18, No.
6, pp. 583{594, December 2002.
-
J. Kim and T. Chen, "Multiple Feature Clustering
for Image Sequence Segmentation", Pattern Recognition
Letters, Elsvier Science B.V., pp. 1207{1217, Vol.22,
July, 2001.
-
G. Cho and T. Chen, "On Mixed PTL/Static
Logic for Low-Power and High-Speed Circuits", VLSI
Design: In International Journal of Custom-Chip Design,
Simulation and Testing, pp. 399-406, Vol.12, No.3,
July, 2001.
-
F. Alzaharani and T. Chen, "On-Chip TEC-QED
Code for Ultra-Large, Single-Chip Memory Systems", International
Journal of Computers and Electrical Engineering, Vol.25,
No.6, December, 2000.
-
V.K. Kim and T. Chen, "On Comparing Functional
Fault Coverage and Defect Coverage for Memory Testing",
IEEE Trans. on Computer-Aided Design of Integrated
Circuits and Systems, Vol.18, No. 11, pp.1672{1683,
Nov. 1999.
-
Y.B. Kim and T. Chen, "Assessing Merged
DRAM/Logic Technology", Integration: The VLSI Journal,
Elsevier Science, Vol.27, No.2, pp179{194, September,
1999.
-
T. Chen, V.K. Kim, and M. Tegethor, "IC
Manufacturing Test Cost Estimation at Early Stages of
the Design Cycle", Microelectronics Journal, Elsevier
Science,
Vol.30, No.8, pp.733{738, August, 1999.
-
T. Chen, V.K. Kim, and M. Tegethor, "IC
Yield Estimation at Early Stages of the Design Cycle", Microelectronics
Journal, Elsevier Science, Vol.30, No.8, pp.725{732,
August, 1999.
-
G. Sunada, T. Chen, and Jian Jin "COBRA:
a 100 MOPS Single-Chip Programmable and Expandable FFT",
IEEE Trans. on VLSI Systems, Vol. 7, No. 2, pp.
174{182, June, 1999.
-
A. Hajjar and T. Chen, "A VLSI Architecture
for Real-Time Edge Linking", IEEE Trans. on Pattern
Analysis and Machine Intelligence, Vol. 21, No.
1, pp.89{94, January, 1999.
-
M. Scharer and T. Chen, "A Tree Matching
Algorithm and VLSI Architecture for Real-Time 2D Object
Classification " Journal Real-Time Imaging ", Elsevier
Science Publisher, Academic Press, Vol. 4, No. 3,
pp.193{202, June, 1998.
-
M. Tegethor and T. Chen, "Simulation Techniques
for the Manufacturing Test of Boards and MCMs", Journal
of Electronic Testing: Theory and Applications (JETTA),
Kluwer Academic Publishing, Vol.10, No 1/2, pp.137{149,
Feb. 1997.
-
F. Alzahrani and T. Chen, "A Real-Time
Edge Detector: Algorithm and VLSI Ar chitecture" Journal
of Real-Time Imaging, special issue on "Special-Purpose
Architectures for Real-Time Imaging", Elsevier Science
Publisher, Academic Press, Vol. 3, No.5, pp.363{378,
Nov, 1997.
-
[PDF]
M. Tegethor and T. Chen, "Sensitivity Analysis of Critical
Parameters in Board Test",
IEEE Design & Test
of Computers, Vol.13, No.1, pp.58-63, 1996.
-
[PDF] M. Tegethor and T. Chen, "A Clustered Yield Model
for SMT Boards and MCMs",
IEEE Trans. on Components,
Packaging, and Manufacturing Technology, Part B: Advanced
Packaging, Vol. 18, No. 4, pp.640-643, November,
1995.
-
X. Wang and T. Chen, "On Performance and
Area Optimization of VLSI Systems." VLSI Design: In
International Journal of Custom-Chip Design, Simulation
and Testing, Vol.3, No.1, 1995.
-
T. Chen and L. Zhu, "An Expandable Column
FFT Architecture Using Circuit Switching Networks", The
Journal of VLSI Signal Processing. Vol.6, No.5,
pp.243-257, 1993.
-
T. Chen and G. Sunada, "Design of A Self-Testing
and Self-Repairing Structure for Highly Hierarchical Ultra-Large
Capacity Memory Chips", IEEE Trans. on VLSI Systems,
Vol.1, No.2, pp.88-97, June, 1993.
-
T. Chen, "From System Design to IC Design
in 14 Weeks { Teamwork Makes It Possible", IEEE Trans.
on Education, Vol.36, No.1, pp.137-140, Feb. 1993.
-
T. Chen, et al, "A Traffic Routing Algorithm
for Serial Superchip System Customization", IEE Proceedings,
Part E, Computers and Digital Techniques, Vol.137,
No.1, pp.65-73, January, 1990.
-
T. Chen, J. Mavor, P.B. Denyer, D. Renshaw,
"Yield Estimation for the Serial Superchip", IEE Proceedings,
Part E, Computers and Digital Techniques, Vol.136,
No.3, pp.187-196, May, 1989.
-
T. Chen, J. Mavor, P.B. Denyer, D. Renshaw,
"A WSI Approach Towards Defect/Fault tolerant Reconfigurable
Serial Systems", IEEE Journal of Solid-State Circuits,
Vol.23, pp.639-646, June, 1988.
-
T. Chen, J. Mavor, P.B. Denyer, D. Renshaw,
"A Superchip Architecture for Implementing Large Integrated
Systems", IEE Proceedings Part E, Computers and Digital
Techniques, Vol.135, No.3, pp.137-150, May, 1988.
-
A. Andrew, A. O'Fallon, and T. Chen, "A
Rule-Based Software Testing Method for VHDL Programs", IFIP
2003 VLSI-SoC Conference, Darmstadt, Germany, Dec. 1-3,
2003.
-
T. Chen and A. Hajjar, "Analyzing Static
Timing Behavior of Coupled Interconnects Using Quadratic
Delay Change Characteristics", 4th International Symposium
on Quality Electronic Design, San Jose, CA, March 24-26,
2003.
-
G. Cho and T. Chen, "Comparative Assessment
of Adaptive Body-Bias SOI Pass Transistor Logic", 4th International
Symposium on Quality Electronic Design, San Jose, CA, March
24-26, 2003.
-
C. Deshpande and T. Chen, "Design of 0.18um
CMOS Test Chip for Power Grid and I/O Characteristics Verification",
Proceedings of ASP-DAC 2003, Jan. 22-24, 2003.
-
G. Cho and T. Chen, "On Single/Dual-Rail
Mixed PTL/Static Circuits in Floating Body SOI and Bulk
CMOS: A Comparative Assessment", 16th International Conference
on VLSI Design. New Delhi, India, Jan. 4-8, 2003.
-
G. Cho and T. Chen, "Application of Genetic
Learning to Pass-Transistor Design and Optimization", 4th
Asia-Pacific Conference on Simulated Evolution and Learning,
Singapore, Nov. 18-22, 2002.
-
G. Cho and T. Chen, "On the Impact of Technology
Scaling On Mixed PTL/Static Circuits", IEEE International
Conf. on Computer Design: VLSI in Computers and Processors
(ICCD), Freiburg, Germany, September, 16-18, 2002.
-
C. Deshpande and T. Chen, "Design of 0.18umm
CMOS Test Chip for Package Models and I/O Characteristics
Verification", 45th IEEE Mid-West Symposium on Circuits
and Systems, Tulsa, OK, August 4-7, 2002.
-
Invited Paper, A. Hajjar and T. Chen, "A
Dynamic Bayesian Based Stopping Criterion: A More Efficient
Statistical Stopping Rule for Simulation-Based Behavioral
Model Verification", 2002 IEEE Int. Workshop on Microprocessor
Test and Verification, Austin, TX, June 6-7, 2002.
-
G. Cho and T. Chen, "On the Impact of Fanout
Optimization and Redundant Burer Removal for Mixed PTL Synthesis
in UDSM CMOS Process", IEEE/ACM 11th International Workshop
on Logic and Synthesis, New Orleans, Louisiana, June 4-7,
2002.
-
Invited Paper T. Chen, "High Performance
Clocking for 10-20 GHz Microprocessors: Issues and Solutions",
IEEE Solid-Sate Circuit Council Workshop on Future 10-20
GHz Microprocessor Designs, in conjunction with International
Solid-State Circuit Conference, San Francisco, CA, Feb.
2002.
-
G. Cho and T. Chen, "Mixed PTL/Static Logic
Synthesis Using Genetic Algorithms for Low Power Applications",
IEEE International Symposium on Quality Electronic Design
(ISQED), San Jose, CA, March, 2002.
-
A. Hajjar and T. Chen, "Improving the Efficiency
and Quality of Simulation Based Behavioral Model Verification
Using Dynamic Bayesian Criteria", IEEE International Symposium
on Quality Electronic Design (ISQED), San Jose, CA, March,
2002.
-
G. Cho and T. Chen,"Technology Mapping for
Low Power SOC Using Genetic Algorithm", IFIP International
Conference on Very Large Scale Integration, Montpellier,
France, Decembre 3-5, 2001.
-
JinSang Kim and T. Chen, "Real-time Video
Objects Segmentation using a Highly Pipelined Microarchitectur",
International Conference Visualization, Imaging, and Image
Processing (VIIP2001), Marbella, Spain, September 3-5, 2001
-
T. Chen, "On the Impact of On-Chip Inductance
on Signal Nets Under the Influence of Power Grid Noise",
DATE: Design Automation and Test in Europe, Munich, Germany,
March, 2001.
-
A. Hajjar, T. Chen, I. Munn, A. von Mayrhauser,
and M Bjorkman, "High Quality Behavioral Verification Using
Statistical Criteria", DATE: Design Automation and Test
in Europe, Munich, Germany, March, 2001.
-
T. Chen, "On the Impact of On-Chip Inductance
When Transitioning From Al to Cu Based Technology", Int.
Symp. on Quality Electronic Design. San Jose, CA, March,
2001.
-
A. Hajjar, T. Chen, I. Munn, A. von Mayrhauser,
and M. Bjorkman, "Stopping Criteria Comparison: Towards
High Quality Behavioral Verification", Int. Symp. on Quality
Electronic Design. San Jose, CA, March, 2001.
-
Jinsang Kim and Tom Chen, "Low-Complexity
Fusion of Intensity, Motion, Texture and Edge for Image
Sequence Segmentation: A Neural Network Approach", IEEE
Int. Workshop on Neural Networks for Signal Processing,
Sydney, Australia, Dec. 2000.
-
A. von Mayrhauser, T. Chen, Jan Kok, C.
Anderson, A. Reed, and A. Hajjar, "On Choosing Test Criteria
for Behavioral Design Verification", IEEE Int. High Level
Validation and Test Workshop, Berkeley, CA, Nov. 2000.
-
Amjad Hajjar, Tom Chen, and A. von Mayrhauser,
"On Statiscal Behavior of Branch Coverage in Testing Behavioral
VHDL Models," IEEE International High Level Design Validation
and Test Workshop, Nov. 2000.
-
Jinsang Kim and Tom Chen, "A VLSI Architecture
for Image Sequence Segmentation Using Edge Fusion," International
Workshop on Computer Architectures for Machine Perception,
Padova, Italy, Sept. 2000.
-
Jinsang Kim and Tom Chen, "Segmentation
of Image Sequences Using SOFM Networks," 15th International
Conference on Pattern Recognition, Barcelona, Spain, Sept.
2000.
-
Jinsang Kim and Tom Chen, "Neural Network
Based Image Sequence Segmentation Using Multiple Features
and Edge Fusion," Advanced Concepts for Intelligent Vision
Systems Symposium, Baden-Baden, Germany, July 2000.
-
Jinsang Kim and Tom Chen, "An Integrated
Approach to Image Sequence Segmentation," IEEE Nordic Signal
Processing Symposium, Vildmarkshotellet, Sweden, June 2000.
-
T. Chen, M. Sahinoglu, A. von Mayrhauser,
A. Hajjar, and C. Anderson, "Achieving the Quality of Verification
for Behavioral Models with Minimum Erort", Proc. 1st IEEE
Int. Symp. on Quality Electronic Design, San Jose, CA, March
20-22, 2000.
-
T. Chen and C. Alkan, "Measuring Routing
Congestion for Multi-layer Global Routing", Proc. 10th Great
Lakes Symposium on VLSI, Chicago, Illinois, March 2-4, 2000.
-
T. Chen, I. Munn, A. von Mayrhauser, A.
Hajjar, "Efficient Verification of Behavioral Models Using
the Sequential Sampling Technique", Proc. 10th Int. Conf.
on VLSI (VLSI99), IFIP, Lisboa, Portugal, December 1-4,
1999.
-
T. Chen, M. Sahinoglu, A. von Mayrhauser,
A. Hajjar, and C. Anderson, "How Much Testing is Enough?
Applying Stopping Rules to Behavioral Model Testing", Proc.
4th IEEE Int. Symp. on High Assurance System Engineering,
Washington D.C., November, 17-19, 1999.
-
J. Kim and T. Chen, "Integration of Multiple
Features Using Back Propagation Neural Networks for Segmentation
of Image Sequences", Proc. of Int. Conf. on Image Science,
Systems, and Technology, pp.65-71, Las Vegas, NV, June,
1999.
-
M. Sahinoglu, A. von Mayrhauser, A. Hajjar,
T. Chen, and Ch. Anderson, "On the Efficiency of a Compound
Poisson Stopping Rule for Mixed Strategy Testing", Proc.
1999 IEEE Aerospace Conference, Snowmass, Colorado, March
6-13, 1999.
-
A. von Mayrhauser, A. Bai, T. Chen, et.
al., "Fast Antirandom (FAR) Test Generation", 3rd IEEE High-Assurance
Systems Engineering Symposium, November 13-14, 1998, Washington,
DC.
-
T. Chen, D. Anderson, et. al. "On Integrating
Multi-Sensory Components In Virtual Environments", Fourth
Int. Conf. on Virtual Systems and MultiMedia, Gifu, Japan,
Nov. 18-20, 1998.
-
A. Bai, T. Chen, et. al., "Fast Antirandom
(FAR) Test Generation to Improve Code Coverage", Quality
Week'98, San Francisco, CA, May 27-30, 1998.
-
T. Chen, P. Young, et. al., "Development
of a Stereoscopic Haptic Acoustic Real Time Computer(SHARC)",
Proceedings of SPIE, Vol. 3295, pp. 171-179, San Jose, CA,
26-29 Jan. 1998.
-
P. Young, T. Chen, et. al., "Legoworld:
A Multisensory Environment for Virtual Prototyping", Proceedings
of SPIE, Vol. 3295, pp. 313-321, San Jose, CA, 26-29 Jan.
1998.
-
T. Chen, P. Young, et. al., "Creating Virtual
Environments Over the Internet", Proceedings of SPIE, Vol.
3295, pp. 322-331, San Jose, CA, 26-29 Jan. 1998.
-
V.Y. Kim, T. Chen, and M. Tegethor, "ASIC
Manufacturing Test Cost Prediction at Early Design Stage",
1997 Int. Test Conference, Washington D.C. November 3-5,
1997.
-
Chien-Chih Chen and Tom Chen, "Modified
Rate-Distortion Function With Optimal Classification for
Wavelet Coding", 1997 Int. Conf. on Image Processing, Santa
Bababra, CA, Oct. 26-29, 1997.
-
A. Hajjar and T. Chen, "A New Real-Time
Edge Linking Algorithm and Its VLSI Implementation", Int.
Conf. on Computer Architectures for Machine Perception (CAMP'97),
Boston, MA, Oct. 20-22, 1997.
-
V.Y. Kim and T. Chen, "IDDQ Testability
Analysis Using Random Test Vectors", 5th International Conference
on VLSI and CAD, Seoul, Korea, Oct. 13-15, 1997.
-
Chien-Chih Chen, John Swanson, and Tom Chen,
"Applying High-Order Polynomial Type Global Constraints
to Stereo Image Coding", 1997 Picture Coding Symposium,
Berlin, Germany, September 10-12, 1997.
-
Chien-Chih Chen and Tom Chen, "Wavelet Coding
By Using Interpolated Rate-Distortion Function and Classified
VQ", 1997 Picture Coding Symposium, Berlin, Germany, September
10-12, 1997.
-
C. Chen, J. Swanson, and T. Chen, "Stereo
Image Coding Using Object-Based Global Constraints", International
Workshop on Synthetic-Natural Hybrid Coding and Three Dimensional
imaging, Rhodes, Greece, Sept. 5-9, 1997.
-
A. Hajjar and T. Chen, "A VLSI Architecture
for Real-Time Edge Linking", IX IFIP Int. Conf. on VLSI,
Gramado, Brazil, August 26-29, 1997.
-
V.Y. Kim and T. Chen, "SRAM Yield Estimation
in the Early Stage of the Design Cycle", 1997 IEEE Int.
Workshop on Memory Technology, Design and Testing, San Jose,
CA, August 11-12, 1997.
-
C. Anderson, A. von Mayrhauser, C.R. Gideon,
T. Chen, and J. Kok, "Test Coverage Prediction of VHDL Models
Using Neural Networks", Annual Oregon Workshop on Software
Metrics, May 11-13, 1997.
-
V.Y. Kim and T. Chen, "Assessing SRAM Test
Coverage for Sub-Micron CMOS Technologies", 1997 VLSI Test
Symposium, April, 27-30, 1997, Monterey, CA.
-
F. Alzahrani and T. Chen, "A Real-Time High
Performance Edge Detector for Vision Applications", 1997
Asia and South Pacific Design Automation Conference, (ASP-
DAC'97) Jan.28 - 31, Makurahi Messe, Chiba, Japan, 1997.
-
Y.B. Kim and T. Chen, "A CMOS Delayed Locked
Loop (DLL) for Reducing Clock Skew to under 500ps", 1997
Asia and South Pacific Design Automation Conference, (ASP-DAC'97)
Jan.28 - 31, Makurahi Messe, Chiba, Japan, 1997.
-
C. Chen and T. Chen, "Hybrid Optimum Classification
inWavelet Transform Coding", 1996 International Symposium
on Multi-Technology Information Processing, Dec. 16- 18,
Hsinchu, Taiwan, 1996.
-
F. Alzahrani and T. Chen, "A Stand-Alone
ASIC for Real-Time Edge-Detection", 8th Int. Conf. on Microelectronics,
Dec. 16-18, Cairo, Egypt, 1996.
-
Y.B. Kim and T. Chen, "A 0.8 ¹m CMOS
Delayed Loop for VLSI Systems with Sub-50ps Clock Skew",
1996 IEEE Asia{Pacific Conference on Circuits and Systems,
(APCCAS'96) Nov.18 - 21, Seoul, Korea, 1996.
-
C. Chen and T. Chen, "Wavelet Coding With
Region Classification Using Low-Complexity Prediction Model",
13th Asilomar Conf. on Signals, Systems, and Computers,
Nov. 3-6, Monterey, CA, 1996.
-
V.Y. Kim, M. Tegethor, and T. Chen, "Yield
Estimation of ASIC Chips at Early Stage of the Design Cycle",
1996 Int. Test Conf., Washington D.C., Nov. 1996.
-
C. Chen and T. Chen, "Wavelet Transform
Coding with Linear Prediction and The Optimal Choice of
Wavelet Basis Functions", 1996 IEEE Nordic Signal Processing
Symposium, Sept. 24-27, Espoo, Finland, 1996.
-
Y.B. Kim and T. Chen, "On System Level Performance
of DRAM/Logic Merged Technology", 1996 Int. Technical Conference
on Circuits/Systems, Computers and Communications, Seoul,
Korea, July 15-17, 1996.
-
Y.B. Kim and T. Chen, "Clock Skew on DRAM/Logic
Merged Technology Based Systems", 1996 Int. Sym. on Circuits
and Systems, May 12-15, Atlanta, GA, 1996.
-
Y.B. Kim and T. Chen, "Assessing DRAM/Logic
Merged Technology", 1996 Int. Sym. on Circuits and Systems,
May 12-15, Atlanta, GA, 1996.
-
C. Anderson, A. von Mayrhauser, and T. Chen,
"Assessing Neural Networks as Guides for Testing Activities",
3rd International Software Metrics Symposium, Berline, Germany,
March 1996.
-
Y.B. Kim, V.Y. Kim, and T. Chen, "A 0.8
¹m CMOS Optical Clock Receiver Design", The 7th International
Conference on Microelectronics, Kuala Lumpur, Malaysia,
Dec. 18-21, 1995.
-
M. Scharer and T. Chen, "A VLSI Architecture
for 2D Object Classification Based on Tree Matching ", CAMP'95:
Computer Architectures for Machine Perception, Como, Italy,
pp.138-143, Sept. 18-20, 1995.
-
M. Scharer and T. Chen, "Object Parts Matching
Using Hopfield Neural Networks", CAMP'95: Computer Architectures
for Machine Perception, Como, Italy, pp.438-442, Sept. 18-20, 1995.
-
C. Morganti and T. Chen, "Graceful Capacity
Degradation for Ultra-Large Hierarchical Memory Structures",
1995 IFIP VLSI Conference, Chiba, Japan, August 30-Sept.
1, 1995.
-
M. Tegethor and T. Chen, "Board Test: Defects,
Fault Coverage, Yield and Cost in Board Manufacturing",
1994 International Test Conference, Washington D.C., October 1994.
-
M. Tegethor and T. Chen, "Manufacturing
Test Simulator: A Concurrent Engineering Tool for Boards
and MCMs", 1994 International Test Conference, Washington
D.C., October 1994.
-
F. Alzahrani and T. Chen, "On-Chip TEC-QED
ECC for Ultra-Large, Single-Chip Memory Systems", 1994 IEEE
International Conference on Computer Design: VLSI in Computers
and Processors, Cambridge, MA, October, 1994.
-
G. Sunada, J. Jin, M. Berzins, and T. Chen,
"COBRA: A 1.2 Million Transistor Expandable Column FFT Chip",
1994 IEEE International Conference on Computer Design: VLSI
in Computers and Processors, Cambridge, MA, October, 1994.
-
M. Tegethor and T. Chen, "On Clustering
of Defects and Yield of SMT Assemblies", 1994 IEEE International
Conference on Manufacturing Engineering, San Diego, CA,
Sept. 1994.
-
G. Sunada and T. Chen, "A Novel DCT Implementation
Using Bit-Serial Arithmetic", 1994 IEEE Data Compression
Conference, Snowbird, Utah, March, 1994.
-
T. Chen and G. Sunada, "SIMSTGEN: A Simulation
Based ATPG For Synchronous Sequential Circuits", Annual
Symposium of Technology Transfer Program, Colorado Advanced
Software Institute, Denver, CO. 1992.
-
T. Chen and G. Sunada, "An Ultra-Large Capacity
Single-Chip Memory Architecture With Self-Testing and Self-Repairing",
ICCD'92, Boston MA, Oct. 1992, Recommended for Best Paper
Award.
-
T. Chen, D. Louderback, and G. Sunada, "Optimization
of the Number of Levels of Hierarchy in Large-Scale Hierarchical
Memory Systems", Proc. of International Symposium on Circuits
and Systems. San Diego, CA, 1992.
-
T. Chen and G. Sunada, "A Self-Testing and
Self-Repairing Structure for Ultra-Large Capacity Memories",
1992 Int. Test Conf., pp.623-628, Sept. 20-24, Baltimore,
MD, 1992.
-
T. Chen and L. Zhu, "A Fast 1024-Point FFT
Architecture", Proc. of 1991 International Conference on
Parallel Processing, 1991.
-
T. Chen, J. Mavor, P.B. Denyer, D. Renshaw,
"A ULSI Architecture for Reconfigurable Serial Systems",
Digest of Technical Papers, 13th European Solid-State Circuits
Conference, Sept. 23-25, 1987, Bad Soden, Germany.
-
T. Chen, P.B. Denyer, J. Mavor, D. Renshaw,"Fault-tolerantWafer
Scale Architectures Using Large Crossbar Switches", Proceedings
of InternationalWorkshop onWafer Scale Integration, North
Holland, 1986.