{"id":7,"date":"2020-02-07T21:05:44","date_gmt":"2020-02-07T21:05:44","guid":{"rendered":"https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/?page_id7"},"modified":"2025-06-23T19:01:54","modified_gmt":"2025-06-23T19:01:54","slug":"home","status":"publish","type":"page","link":"https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/","title":{"rendered":"Home"},"content":{"rendered":"<article id=\"post-40\" class=\"post-40 post type-post status-publish format-standard hentry category-uncategorized\">\n<div class=\"inside-article\">\n<header class=\"entry-header\">\n<h2 class=\"entry-title\"><a href=\"https:\/\/www.engr.colostate.edu\/SPHPC19\/2018\/01\/30\/40\/\" rel=\"bookmark\">About SPHPC<\/a><\/h2>\n<\/header>\n<div class=\"entry-content\">\n<p>Silicon photonics has emerged as a promising solution to realize high performance computing (HPC) systems required in the Big Data era. Having various applications in the domains of HPC, data centers, sensors and bio-sensing, aerospace, etc., it has attracted researchers from academia and industries in different fields to explore different benefits and challenges of this technology. As an emerging area, it demands multidisciplinary collaborations and contributions, from material science and engineering, to realizing low-loss CMOS compatible components, as well as software CAD and design tools to explore the design space of the resulting complex devices and systems.<\/p>\n<p>The\u00a0<strong>North American Workshop on Silicon Photonics for High Performance Computing (SPHPC)<\/strong>\u00a0is bringing together experts in Silicon Photonics and in High Performance Computing (HPC architects, interconnect architects, HPC systems modeling) to discuss the needs for Silicon Photonics based HPC interconnects, and the main challenges that must be addressed to accelerate their development. It is comprised of invited talks of the highest caliber from both academia and industry as well as from different disciplines. This is the event for meeting professionals in the field as well as exchanging and exploring new ideas.<\/p>\n<p align=\"justify\">In general, we expect to address and discuss the following questions at SPHPC:<\/p>\n<ul>\n<li>Are 200G or 400G links and switches absolutely required in the next years? Or can double- or quad-rail 100G be satisfying solutions?<\/li>\n<li>Is the lack of interconnect bandwidth really an obstacle for HPC system scaling?<\/li>\n<li>Are parallel programmers bracing for bandwidth scarce environments (as they are preparing for the end of Moore\u2019s Law)? Or are they betting on progresses in photonics?<\/li>\n<li>Is low $\/Gb\/s the only goal or are there other metrics to optimize for, e.g. bandwidth density, energy efficiency?<\/li>\n<li>Are HPC system architects well aware of the true potential, and true limitations, of silicon photonics?<\/li>\n<li>Do silicon photonics experts understand well what is and isn\u2019t required for HPC interconnects?<\/li>\n<li>Is interconnect power consumption an important issue? Or is it dominated by the cost issue anyway?<\/li>\n<li>When will silicon photonics beat (in overall value for money) copper based back-plane links?<\/li>\n<li>Can silicon photonics ever beat copper for short-distance links, e.g. to memory?<\/li>\n<li>Can silicon photonics do better than VCSELs based links?<\/li>\n<li>How important is bandwidth density (in Gb\/s per silicon area) in the context of integrated photonics?<\/li>\n<li>Can ring resonators really replace Mach-Zehnders or EAM for modulation in practice, even in challenging thermal environments?<\/li>\n<li>Is it possible to obtain high bandwidth density with Mach-Zehnders or EAM?<\/li>\n<li>Can coherent systems meet ultra-low cost requirements? Are there a viable option for high energy efficiency, low cost links?<\/li>\n<li>Are EPDA tools ready for prime-time?<\/li>\n<li>Isn\u2019t the bottleneck in the link between the ASIC and the transceiver after all?<\/li>\n<li>How can electrical drivers challenges (SERDES, TIA, coding) better be taken into account in the link design?<\/li>\n<li>How can one expose more the photonic community to electrical drivers challenges?<\/li>\n<li>Is silicon photonic fundamentally capable of beating\u00a0 copper for short distances? Or will EO\/OE conversion overheads always be a liability?<\/li>\n<li>Is there a realistic solution for low-cost packaging and assembly of ASICs with integrated photonics?<\/li>\n<li>Is it a must to have the laser co-integrated? Or can we leave with external supply? Or is it the best solution after all (e.g. given thermal challenges)?<\/li>\n<li>If silicon photonic links eventually beat copper in both cost and power terms for few cm links, will it enable a computer architecture revolution?<\/li>\n<li>Is there really room for optical switching in HPC? How can optics beat electrical packet switches showing only tens of nanosecond of latency?<\/li>\n<li>In general, what are the hottest issues and challenges? Which ones must be addressed in priority?<\/li>\n<\/ul>\n<\/div>\n<\/div>\n<\/article>\n<article id=\"post-313\" class=\"post-313 post type-post status-publish format-standard hentry category-uncategorized\">\n<div class=\"inside-article\">\n<header class=\"entry-header\">\n<h2 class=\"entry-title\"><a href=\"https:\/\/www.engr.colostate.edu\/SPHPC19\/2019\/02\/16\/keynote-talks-at-sphpc19\/\" rel=\"bookmark\">Keynote Talks at SPHPC19<\/a><\/h2>\n<\/header>\n<div class=\"entry-content\">\n<table>\n<tbody>\n<tr>\n<td><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-58 size-medium\" src=\"https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-content\/uploads\/sites\/3\/2025\/06\/Li-Diang-300x300.jpg\" alt=\"Li Diang\" width=\"300\" height=\"300\" srcset=\"https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-content\/uploads\/sites\/3\/2025\/06\/Li-Diang-300x300.jpg 300w, https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-content\/uploads\/sites\/3\/2025\/06\/Li-Diang-150x150.jpg 150w, https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-content\/uploads\/sites\/3\/2025\/06\/Li-Diang.jpg 360w\" sizes=\"auto, (max-width: 300px) 100vw, 300px\" \/><\/td>\n<td><strong>Keynote 1:<\/strong>\u00a0Dr. Li Diang, HPE, USA<\/p>\n<p><strong>Title:\u00a0<\/strong>Silicon-Plus Photonics Integration for High Performance Computing and Beyond<\/td>\n<\/tr>\n<tr>\n<td><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-59 aligncenter\" src=\"https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-content\/uploads\/sites\/3\/2025\/06\/Mike_Haney.png\" alt=\"Mike Haney\" width=\"144\" height=\"158\" \/><\/td>\n<td><strong>Keynote 2:<\/strong>\u00a0Dr. Michael Haney, U.S. Department of Energy (DoE), ARPA-E Program Director<\/p>\n<p><strong>Title:\u00a0<\/strong>The ARPA-E ENLITENED Program \u2013 Enabling Transformative Datacenter and HPC Networks with Integrated Photonics<\/td>\n<\/tr>\n<tr>\n<td><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-60 size-medium\" src=\"https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-content\/uploads\/sites\/3\/2025\/06\/Tom-Daspit-244x300.jpg\" alt=\"Tom Daspit\" width=\"244\" height=\"300\" srcset=\"https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-content\/uploads\/sites\/3\/2025\/06\/Tom-Daspit-244x300.jpg 244w, https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-content\/uploads\/sites\/3\/2025\/06\/Tom-Daspit-834x1024.jpg 834w, https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-content\/uploads\/sites\/3\/2025\/06\/Tom-Daspit-768x943.jpg 768w, https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-content\/uploads\/sites\/3\/2025\/06\/Tom-Daspit-1251x1536.jpg 1251w, https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-content\/uploads\/sites\/3\/2025\/06\/Tom-Daspit-1668x2048.jpg 1668w, https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-content\/uploads\/sites\/3\/2025\/06\/Tom-Daspit.jpg 1710w\" sizes=\"auto, (max-width: 244px) 100vw, 244px\" \/><\/td>\n<td><strong>Keynote 3:\u00a0<\/strong>Dr. Tom Daspit, Mentor Graphics (A Siemens Business), USA<\/p>\n<p><strong>Title:\u00a0<\/strong>Integrated Photonics \u2013 Are the design tools ready for HPC Design?<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>Get Your Hands on SiPh Device Simulation and Fabrication<\/strong><br \/>\nSPHPC19 hosts a \u201cLuncheon with Lumerical\u201d session, included in SPHPC registration, during which attendees will learn about Lumerical tools\u2019 new capability for\u00a0<strong>Photonics Inverse Design<\/strong>, using two techniques: parametric shape based and topology optimization. Using Lumerical tools, which will be made available to SPHPC19 attendees during this session, an example design will be discussed that can be modified to create an optimal design using Photonic Inverse Design. As an added bonus at no cost to SPHPC19 attendees, you will be able to submit your design for fabrication by Electron-Beam Lithography Facility at University of British Columbia (UBC).<\/p>\n<\/div>\n<\/div>\n<\/article>\n<article id=\"post-316\" class=\"post-316 post type-post status-publish format-standard hentry category-uncategorized\">\n<div class=\"inside-article\">\n<header class=\"entry-header\">\n<h2 class=\"entry-title\"><a href=\"https:\/\/www.engr.colostate.edu\/SPHPC19\/2019\/02\/16\/invited-speakers\/\" rel=\"bookmark\">Invited Speakers<\/a><\/h2>\n<\/header>\n<div class=\"entry-content\">\n<p>We are excited and delighted to welcome the following colleagues at SPHPC:<\/p>\n<pre>Jelena Vuckovic, Stanford, USA\u00a0\r\nS. J. Ben Yoo, UC Davis, USA \r\nDi Liang, HPE, USA\r\nTom Daspit, Mentor Graphics, USA\r\nMark Wade, Ayar Labs, USA\r\nTakahiro Nakamura, PETRA, Japan\r\nArmin Tajalli, University of Utah, USA\r\nMichael Haney, DoE\/ARPA-E Program, USA\r\nSeth Kruger, AIM Photonics, USA\r\nTian Gu, MIT, USA\r\nAaron Zilkie, Rockley Photonics, USA\r\nChi Xiong, IBM T. J. Watson Research Center, USA\r\nJames Pond, Lumerical, Canada\r\nIan Karlin, Lawrence Livermore National Laboratory (LLNL), USA\r\nBenoit Charbonnier, CEA-LETI, France\r\nJohn Kim, Korea Advanced Institute of Science and Technology (KAIST), Korea\r\nAjay Joshi, Boston University, USA\r\nLieven Verslegers, Google, USA\r\nJohn R. Cary, University of Colorado at Boulder and Tech-X Corporation, USA\r\nClint Schow, University of California at Santa Barbara, UCSB, USA<\/pre>\n<\/div>\n<\/div>\n<\/article>\n","protected":false},"excerpt":{"rendered":"<p>About SPHPC Silicon photonics has emerged as a promising solution to realize high performance computing (HPC) systems required in the Big Data era. Having various applications in the domains of HPC, data centers, sensors and bio-sensing, aerospace, etc., it has attracted researchers from academia and industries in different fields to explore different benefits and challenges &#8230; <a title=\"Home\" class=\"read-more\" href=\"https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/\" aria-label=\"Read more about Home\">Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-7","page","type-page","status-publish"],"_links":{"self":[{"href":"https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-json\/wp\/v2\/pages\/7","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-json\/wp\/v2\/comments?post=7"}],"version-history":[{"count":6,"href":"https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-json\/wp\/v2\/pages\/7\/revisions"}],"predecessor-version":[{"id":63,"href":"https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-json\/wp\/v2\/pages\/7\/revisions\/63"}],"wp:attachment":[{"href":"https:\/\/www.engr.colostate.edu\/SPHPC\/2019\/wp-json\/wp\/v2\/media?parent=7"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}