1. Design Environment Setup

Please download this file (sample_cshrc) to your home directory and type "source sample_cshrc" ( "source ~/sample_cshrc") in your home (current working) directory. Read the basic_unix_howto.pdf for how to use the Sunrays and work on remote HPUX machines.

2. Run Checkmate & DRC Checking

2.1) CHECKMATE
 If you have  following error when you run "checkmate [design_name]",  you need to download a file (example.mctl ) to your current working directory and modify it.

• Ckeckmate Error message example :

        The syntax for MASKCHECK is :
        MASKCHECK layout_db cell ......................
                                   - or -
        MASKCHECK control_file_pathname [-mem X] [-mmem X] [-smem X]
        The items enclosed in [] are optional, but if used, they must ..........
 

• Procedure to modify example.mctl file

1. Type "mv example.mctl  [design_name].mctl"  at unix prompt.  /* do not include [ and/or  ] */
2. Edit [design_name].mctl as follows :

Layout_DB = [your_current_working_directory_name (fullpath)]/[design_name].gds
Cell to process          = [design_name]
SV_DB                    = [design_name].svdb
Output design name          = [design_name].gds
drc diagnostics file        = [design_name].drc
erc diagnostics file        = [design_name].erc
3. Save the file and run "checkmate" .

• Editing .DRC file & Debugging Design Rule errors

1. If you see any lines contains "date time year", change the year to "2000" or "1999"..

RULE 69
1 1 1 Sep  5 23:41:25 19100
POLY OVERLAP OF CONP = 2.0 ' RULE 8.5.7 NH
               |
               V
RULE 69
1 1 1 Sep  5 23:41:25 2000
POLY OVERLAP OF CONP = 2.0 ' RULE 8.5.7 NH
2. Save .DRC file
3. Open  layout using IC Graph
4. Click ICRules -> DataBase -> Restore , select [design_name].DRC file and click OK.
5. Click First to display the first error , and click Next to see next error.

After the simulation is complete, select the signal nets or ports in the schematic window and use the top menu bar to access the charting  functions:

A dialog box appears and the signal name for A will appear in the name field. Press the [A vs. B] button and both A and B name fields are filled out for you. If you want to reverse the order of the names [A becomes B, etc] type the names by hand.

Click on OK and the chart appears. There are other ways of doing this or even more complex charts using the WaveForm Processor.
This allows you to create expressions including many mathematical functions. It can also handle waveform databases from simulations or generate new ones by processing, etc.

The waveform processor is invoked through pull-down menu:

3. Printing Method on Mentor Graphics Tools

3-1) Add the following environment variable in your  .cshrc file (this file is located in your home directory).

4. Define 2-phase non-overlap clocks in L sim

  startup set Initial_Probes off
  startup set Prop off
  # startup set Initial_Sim off
  # startup set Pseudo_Switch_Delay YES
  # startup set Transistor_Delay 0.2ns

  p ck1 ck2 ckear ce CNTL0 CNTL1 a[0] a[1] a[2] a_bar[0] a_bar[1] a_bar[2] co enb a0 a1 a2 a3

  clockdef main 25
  clockon main
  subclock main ck1 skew 0% 0%,0 3%,t"{.5"} 45%,t"{.5"}"
  subclock main ck2 skew 0% 0%,0 53%,t"{".5"} 95%,t"{.5"}"

  alias init "vforce 5 clear; vforce 0 ce; s 62; vforce 0 clear; vforce 5 ce"
  alias con1 "vforce 0 CNTL0,CNTL1"

  alias run "con1;init; s 5000"
  run
 

5. LINKS THAT MIGHT BE HELPFUL

Mentor Graphics IC Layout & Verification Tutorial http://www.ele.uri.edu/Research/cherry/mentor_tutorial/ Mentor Graphics Tutorials http://ge.ee.wustl.edu/dzar/tutorials.html Mentor Graphics QuickHDL http://users.ece.gatech.edu/~schimmel/cmpe4500/vhdl.html Mentor Graphics QuickVHDL Tutorial http://www.scudc.scu.edu/mentortu/mg_qvhdl.html VHDL Simulation with QuickHDL http://www.cs.uno.edu/~mahdi/csci6330/qvhdl/ VHDL Page http://www.mark-itt.ru/~vic/VHDL/